Hi Scott.
Im a bit late on this thread. Well other things you see. Nevertheless, Ive been reading the ePAPR which looks more like a document which describes the guidelines rather than a description of something existing. More like a POSIX document perhaps?
I also see many references to the term 'Client Program' all the time. Does this client program refer to the bootloader aka the first program to run when the chip is out of reset or does it refer to the program that will eventually run on the chip? Which could be anything from a bare-metal Kind of OS or a full fledged OS like Linux.
Now coming on to the actual document, section 5.3 in ePAPR talks of Initial Mapped Areas(IMA) areas which I believe are mapped by default to certain portions of the memory. Another reference to IMAs was found in the freescale powerpc programming environments manual section 7.3.1.1 called Predefined Physical Memory Locations . Do both these sections in these two documents refer to the same concept?
Here are the predefined physical memory locations
The freescale document says:
Four areas of the physical memory map have predefined uses. The first 256 bytes of physical memory (or if MSR[IP] = 1, the first 256 bytes of memory located at physical address 0xFFF0_0000) are assigned for arbitrary use by the operating system. The rest of that first page of physical memory defined by the vector base address (determined by MSR[IP]) is used for interrupt vectors or reserved for future interrupt vectors. So it means that when the process comes out of reset (which can be looked at as interrupt) it vectors into memory area 2 which can be either 0x0000_0100 or 0xFFF0_0100. Am I right here? If so, can this memory region be categorized as a Boot IMA as per the ePAPR document?
Now doing a quick scan of 0xFFF0_0000 under the arch/powerpc folder didn't quite turn up anything concrete:
$ grep -iwr 0xFFF00000 .
./boot/dcr.h:#define EBC_BXCR_BAS 0xfff00000
./boot/dts/mgsuvd.dts: ranges = <0 0xfff00000 0x00004000>;
./kernel/cputable.c: .pvr_mask = 0xfff00000,
./kernel/cputable.c: .pvr_mask = 0xfff00000,
./platforms/powermac/cache.S: * that we can read from ROM at physical address 0xfff00000.)
./platforms/powermac/pci.c: reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
./sysdev/fsl_pci.c: rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
./sysdev/fsl_pci.c: rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
However as per the u-boot source code, the reset vector address is 0xFFFF_FFFC. They have a #define within u-boot.lds the loader script for the mpc85xx which explicitly defines the reset vector address to be 0xFFFF_FFFC. This address is not however not mentioned at all in the ePAPR. Ive tried looking into the programming references manual, the e500mc reference manual and the programmer's reference manual but to no avail. How did u-boot arrive at this address? The only reference I could find for this address is in section 6.6 of the e500mc reference manual which is for the TLB states after reset. Is there a memory map for the e500 family of processors that I could find somewhere in these manuals?
Secondly, I see in ePAPR in section 5.4 entitled CPU Entry points requirements that the initial register values must be as such:
However, when I see head_fsl_booke.S, I see the following comment:
/* As with the other PowerPC ports, it is expected that when code
* execution begins here, the following registers contain valid, yet
* optional, information:
*
* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
* r4 - Starting address of the init RAM disk
* r5 - Ending address of the init RAM disk
* r6 - Start of kernel command line string (e.g. "mem=128")
* r7 - End of kernel command line string
*
*/
Why is there such a discrepancy? The only thing common is the content of register r3. Since board info structure pointer and device tree image seem to be suggest the same thing. No?
Lastly there seems to be quite a few differences between the 'Programming Environments Manual' aka MPCFPE32B and the 'Programmers' Reference Manual (for the e500 family)' aka EREF_RM. The latter one is more specific and has been published at a later date (2011 vs 2005 for the former). Like for instance the programming manual defines such things as the segment registers; some of the MSR bits are different between the two - Former has IR and DR for instruction and data translation whereas the latter does not seem to have these bits and instead defines IS and DS. Im sort of confused here. Which one should I be referring to and why? Ive noticed that it is rather hard to find the right document for the right answer unlike MIPS but then it could just be a case of a rookie finding his way around. Like in the above example, depending on which one I refer to, many things change. In fact the entire address translation mechanism seems to be differently shown in these two documents. Your help would be really appreciated at this moment :smileycry:
