Trying for support of phyless connection for DTSEC1 for P1023.

[sarathchandra]

Hi all,

           I am working on a P1023 integrated board. Where DTSEC2 connected to a Ethernet PHY (that goes via Serdes-lane 03.... / lanes numbers from 0 to 3) is working fine.

           But DTSEC1(that goes via SerDes lane 02) to ARM based marvel switch, without any PHY connection between them.

          I checked switch is working fine. SerDes-lane 02 connection is good.

          I removed the "auto negotiation enable" inorder to support phyless connection at uboot and still we have problem.

-------------------------------------------------
drivers/net/tsec.c
I removed TBICR_ANEG_ENABLE option from TBICR_ANEG_ENABLE macro
The edited one looks like this.
#ifndef CONFIG_TSEC_TBICR_SETTINGS
  #define CONFIG_TSEC_TBICR_SETTINGS ( \
                TBICR_PHY_RESET \
/*              TBICR_ANEG_ENABLE     */
                | TBICR_FULL_DUPLEX \
                | TBICR_SPEED1_SET \
                )
#endif /* CONFIG_TSEC_TBICR_SETTINGS */
----------------------------------------------------

             Is there is any better ways to resolve the issue.

Regards,

Sarath

[sarathchandra]

Thank you lunminliang. Now i am able to connect switch in U-Boot and soon kernel bring up I lost connection.

Any how I am making changes in DTS according to your referred link. Update you soon I got connectivity.

[lunminliang · Accepted solution]

Welcome. And more comment from application:

there should be some setting in the switch side, to have the switch port to work at phy-less mode. In other words, make both the DTSEC and switch port to work at MAC-to-MAC mode.

You could check the link status on both the TBI MDIO register at DTSEC side, and switch port side, to make sure both side has the link-up status.

Then set the switch port to work at echo mode/loopback mode to narrow down the problem.

[sarathchandra]

Resolved the issue. Thanks for your presence.

Regards,

Sarath

[jalbert]

How did you solve this? Was the above change in drivers/net/tsec.c necessary?

Cheers,

Joerg

[sarathchandra]

Hi Albert,

              Make sure the settings

Step 1:

drivers/net/tsec.c

I removed TBICR_ANEG_ENABLE option from TBICR_ANEG_ENABLE macro

The edited one looks like this.

#ifndef CONFIG_TSEC_TBICR_SETTINGS

  #define CONFIG_TSEC_TBICR_SETTINGS ( \

                TBICR_PHY_RESET \

/*              TBICR_ANEG_ENABLE     */

                | TBICR_FULL_DUPLEX \

                | TBICR_SPEED1_SET \

                )

#endif /* CONFIG_TSEC_TBICR_SETTINGS */

Step 2:

In your dts change the tsec of your mdio to tbi PHY.

mdio0: mdio@e1120 {

                #address-cells = <1>;

                #size-cells = <0>;

                compatible = "fsl,fman-mdio";

                reg = <0xe1120 0xee0>;

                interrupts = <26 1 0 0>;

                tbi0: tbi-phy@8 {

                    reg = <0x8>;

                    device_type = "tbi-phy";

                };

};

Check you PHY address in the following:

=> mii info

PHY 0x04: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x05: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x06: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x07: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00, 1000baseX, FDX

PHY 0x09: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x0A: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

PHY 0x0B: OUI = 0x5043, Model = 0x1C, Rev = 0x00,  10baseT, HDX

In this ours is PHY 0x08.

[lunminliang]

You may take a look at thisDevice Tree (.dts) configuration for eTSEC2 in SGMII/Serdes mode