P2020 supports only differential DQS - refer to the P2020 RM, 8.4.9 DDR SDRAM control configuration 2 (DDR_DDR_SDRAM_CFG_2), 4–5 DQS_CFG.
> if I set bit10 of EMR1 register to 0, has the DQS# signal been enabled ?
The DQS# will be enbled for the DDR2 SDRAM chips.