I have a problem with a custom P4080 design. Using the kernels provided via the git repository I can either use the DPAA ethernet (with fsl-sdk-v1.3.x branch) or I can use PCIe (with fsl-sdk-v1.4 branch). The device tree and kernel config is the same in both version.
PCIe is connected via SerDes as are the Ethernet PHYs.
With SDK 1.3.x:
When I select CONFIG_SATA_SIL24 to use onboard the Silicon Image 3124 or I active USB I get a Kernel OOPS. If I deselect both drivers the board boots fine and has working network.
With SDK 1.4:
USB and SIL24 are working but none of my DPAA ethernets comes alive.
Doing a Git bisect wasn't really helpful either.
Does anyone experience a similar problem?
Thanks in advance,
This in general looks like a hard reset configuration issue. Parallel Ethernet ports share pins with USB, SGMIIs can potentially conflict with PCIe.
Therefore, technical support's suggestion is to ensure that RCW does select the interfaces you wish to utilize and that you don't attempt to use port combinations that are mutually exclusive.
Details can be found in P4080RM, sections 3.5 and 4.6.4.
Also, please be informed that Silicon Image 3124 is not a Freescale product, we did not test any driver for it with any version of the SDK. If there are issues with the driver for that peripheral, our suggestion is to contact the driver maintainer or the chip manufacturer.
I know that you has an open Service Request for a potential issue for their device tree. Checking a device tree source code is a time-consuming procedure, you're suggested to wait for response to SR 1-1083755035.
We sucessfully got VxWorks running with PCIe and Ethernet. So it can't be a RCW issue.
When booting Linux with active Ethernet I get machine check exceptions on initialization of the PCIe devices (note not @ PCIe enumeration stage but later).
Apart from the Machine Check Exceptions I also get messages from the kernel's error detection and correction subsystem:
PCIE error(s) detected
PCIE ERR_DR register: 0x00000020
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
Anyone out there with an idea?