In the manual P1022RM there is description of PCI Express Controller Internal CSRs at pci configuration 0x400 to 0x6FF .
Is there a public descriptions of that registers may it only be used for debug purpose.
Micha
The implemented registers are described in the processor's RM starting from "16.11.16 LTSSM State Status Register (LTSSM_State_Status_Register)".
