P4080 illegal op-code exception

[bobperry]

I have a P4080 system which is generating random exceptions.  The exception is a program fault and the ESR indicates an illegal op-code.  I did find that the instruction cache entry for this address was NULL.  Infact, the entire way was all NULL although looking at that memory address should valid instructions.  i have now disabled the instruction cache and also the data cache and i am still seeing the same fault.  The fault occurs in random places and also at random times.  I can execute the same code 100 times without fault and then get a series of faults all in different memory locations.  However, the dumping memory at the location of SRR0 shows valid op-codes.  Can anyone throw any light on what the problem maybe.

[bobperry]

I have found the issue.  The running code was executing in memory which was coherent.  The problem was that the code was written to that core's memory via Linux running on another core.  This lead to caching issues between the two cores.  By setting up a TLB on the executing core to cache inhibit during upload and then switching to coherent before executing has fixed the fault.

[scottwood]

A better approach is to always map RAM as cacheable and coherent, and to make sure that you clean d-cache and invalidate i-cache (as specified in the architecture) when you modify/load code.

[bobperry]

Hi Scott,

Do you have example code demonstrating this?

[scottwood]

Section 1.8 "Instruction Storage" of Book II of Power ISA V2.06B says to use the sequence "dcbst X; sync; icbi X; isync" for each modified cache line.

[Pavel]

Usually similar problem detected if incorrect memory operations happen. Test your board using a memory test. Use L2 cache as SRAM for this test. NXP CodeWarrior support configuration for using L2 cache as SRAM see attached initialization file.

Have a great day,
Pavel

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