P2041 boot from Nor flash CS0 timing

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P2041 boot from Nor flash CS0 timing

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wxwangyan
Contributor I

  I am having a p2041 processor card.

i have set the hard corded rcw value of scr_rcw_cfg 11000 16 bit nor flash now, So P2041 will work at 600MHz platform,LCLK0 will be 18.75MHz I captured the waveform for CS0 from P2041. The CS0 signal's active "0" level time is about 110ns when boot up from nor flash, the same as signal LGPL2.

 Chapter 13 Enhanced Local Bus Controller, Table 13-16. Reset value of OR0 Register ,  The GPCM value of OR0 will be 

0000_0FF7, so that The CS0 signal's active "0" level time will be tCSRP=(1+2*SCY) ,16* LCLK0 will be about 0.85us.

But i measured the timing of CS0 boot time is 110ns, pls help to resolve it? 

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alexander_yakov
NXP TechSupport
NXP TechSupport

Please verify pull-up on pin L2 "LGPL4/LGTA/LUPWAIT/LPBSE" is this pull-up is present, properly mounted and has desired value.


Have a great day,
Alexander
TIC

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wxwangyan
Contributor I

attached waveform of CS0 from P2041cs0_2.pngcs0_1.png

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