P2041 DDR RCW MEM_PLL_RAT incorrect

[bradbrook99]

Hello,

I am having some trouble setting up the PLL for the DDR controller on the P2041. 

The RCW memory map in the users manual has MEM_PLL_CFG and MEM_PLL_RAT mapped to

bits 8-9 and 10-14.  When using this mapping, the controller frequency is not what

is expected.  I found that by shifting the two fields one bit to the left

MEM_PLL_CFG(to bits 7-8) and MEM_PLL_RAT(to bits 9-13)in the RCW memory map corrects the

problem(or seems to).

I'm just wondering anyone else has encountered this problem and if this is the correct fix.

[bradbrook99]

No change.

[bradbrook99]

I found a clue in the errata (P2041CE-TP: entry A-004759)

A-004759: MDVAL may not assert for writes in half-speed mode 

Affects: DDR 

Description: When the DDR controller internal logic is operating in half-speed mode (i.e. Half-speed mode 

is set when Reset Configuration Word bit 232 DDR_RATE field = 0), then the MDVAL signal 

may not assert during write transactions. 

Impact: The MDVAL signal may not function when memory controller is in half-speed mode. 

Workaround: A strobe signal (DQS) can be used instead of MDVAL signal to observe/indicate a valid write/ 

read transaction. 

Fix plan: No plans to fix

I cannot find any other reference to “half-speed mode” in the other documents but it sounds like it may be a viable cause.  I’ll try setting this bit to a 1 and post the results.

[bradbrook99]

I am using silicon revision 2.0.  Could that have something to do with it?

[Bulat]

It is hardly possible. Can you read all RCW words using a debugger?

Some signals in the HW specifications are listed with note 31, "pin must NOT be pulled down during power-on reset", see table 1. Can you go through the schematics and check actual connection of all these signals?

[bradbrook99]

I will check the schematic.  We have so far been unsuccessful getting the memory controller to initialize using U-boot but, when it hangs, I have noticed that the clock frequency is correct.  And the clock frequency on the RDB is also correct using the values from the datasheet.  The frequency problem I am having must be something missing in the debugger's config file.  I'll start a new thread for that one.

Thanks for the help everyone.

[bradbrook99]

I'm getting closer but not out of the woods yet.  When I calculate the values based on data rate and set the "CFG" as specified in the manual, I am still not getting the expected frequency on the MCK pins.

12140000 (10:1,96.7 cutoff)  833.3MT/s  frequency  417MHz ------------------  measured 417MHz (this is correct) 

12580000 (12:1, 80.6 cutoff)  1000MT/s frequency  500MHz --------------------- measured 250MHz (half of expected) 

12600000 (16:1, 60MHz cutoff) 1333MT/s frequency 666MHz -------------------- measured 333MHz (half of expected) 

If I invert the CFG bits for the two incorrect results, the output frequency is corrected. 

12180000 (12580000 with CFG bit=0) ------------------ measured 500 MHz  

12200000 (12600000 with CFG bit=0) --------------------- measured 666MHz

Both of these results disagree with the manual but yield what seems to be the correct frequency. 

[Bulat]

This looks strange. Make sure that RCW bits 184, 232 and 234 are set properly, see details in section 3.1.5 of the P2041EC. Note, RCW value 0x1260000 is default on the P2041RDB, everything works properly. Here is u-boot log for sure:

U-Boot 2013.01-04009-g7bcd7f4 (Mar 19 2013 - 18:46:53)

CPU0:  P2041E, Version: 1.1, (0x82180111)

Core:  E500MC, Version: 2.2, (0x80230022)

Clock Configuration:

       CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,

       CCB:750  MHz,

       DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz

       FMAN1: 583.333 MHz

       QMAN:  375 MHz

       PME:   375 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

Board: P2041RDB, CPLD version: 4.0 vBank: 1

Reset Configuration Word (RCW):

       00000000: 12600000 00000000 241c0000 00000000

       00000010: 648ea0c1 c3c02000 de800000 40000000

       00000020: 00000000 00000000 00000000 d0030f07

       00000030: 00000000 00000000 00000000 00000000

...

[bradbrook99]

Ok that makes more sense.  I wasn't aware it was "DDR data rate" to sysclk ratio.  Thanks for the help.

Regards,

Chris

[bradbrook99]

Hi guys,

Thanks for the response.  Yiping, the RCW value 12600000 does in fact coincide with 16:1 with a cutoff of 60 MHZ according to the users manual.  However, this can’t be correct according to the max ddr frequency. Even if using the minimum sysclk frequency of 66.6MHz, a 16:1 ratio would drive the ddr frequency to 1065 MHz which is beyond the max frequency of 667MHz(1333MT/s) from table 100 of EC manual.   

My conclusion was drawn based on trial and measurement.  I am using an 83.3MHz sysclk for which there were three supported ddr speeds. 417, 500, and 666MHz.  I tried each of the below RCW values and measured the ddr clock frequency(on the MCKn output) for each value. 

120a_0000 (5:1, 96.7 cutoff) –> Measured frequency = 416 MHz (correct but I think this one was just a coincidence)  

1258_0000(6:1, 80.6 cutoff) –> Measured frequency = 250MHz. 

1210_0000(8:1, 120 cutoff) –> Measured frequency = 333MHz. 

Trying multiple other values and measuring, I was able to find the correct combinations that would eventually output the correct frequency.  After inspecting and comparing the results I noticed that the working values could be realized by shifting the values indicated in the users manual for bits 8-14 one bit to the left.  After doing this, all three of the results came out correct. 

1214_0000 (120a_0000 with bits8-14 shifted left) –> Measured frequency = 417 MHz 

12b0_0000 (1258_0000 with bits8-14 shifted left) –> Measured frequency = 500 MHz 

1220_0000 (1210_0000 with bits8-14 shifted left) –> Measured frequency = 666 MHz

Is there any way you can verify this? 

Regards,

Chris

[Bulat]

Actually your tests and measurements confirm that the manual is correct. Note, MEM_PLL_RAT defines "DDR data rate' to SYSCLK ratio, not MCK to SYSCLK ratio. This is clearly stated in section 3.1.5 of the P2041 HW specifications (P2041EC). If your SYSCLK is 83MHz and you are going to get 1333MT/s data rate, you need to set MEM_PLL_RAT to 1333:83 = 16:1, that is 0b1_0000 (RSW bits 10-14 for sure). MEM_PLL_CFG (RCW bits 8-9) should be set to 0b01 since SYSCLK frequency is higher than the cutoff (60.4MHz).

Hopefully this helps.

[frankcastanho]

Bulat, while paragraph 3.1.5 clearly states MEM_PLL_RAT defines "DDR data rate'  section 3.1 of the same P2041 HW specifications muddies the water causing the confusion

"The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or

from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex

PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR Controller PLL Ratios.”

Recommend you change DDR Clock above to DDR controller clock, also add note the DDR clock device is 1/2 this controller clock.  Basically 2 sections of the document counterdict each other (i.e.) not clear as you stated.

[yipingwang]

Hello Chris &Karymov,

On P2041RDB the default SysClk is 83.333, RCW 12600000 (16:1, 60.4 MHz cutoff), DDR Data Rate 1.333GT/s, frequency 667MHz.

The following is what I verified with QCS tool which is designed based on P2041 user manual.

120a_0000(5:1, 96.7 MHz cutoff)    DDR Data Rate  417MT/s    frequency  208MHz

1258_0000(12:1, 80.6 cutoff)            DDR Data Rate  1000MT/s  frequency  500MHz

1210_0000(8:1, 120 cutoff)                DDR Data Rate  666.7MT/s  frequency  333MHz

1214_0000(10:1,96.7 cutoff)            DDR Data Rate  833.3MT/s  frequency  417MHz

12b0_0000 invalid

1220_0000(16:1, 60.4 cut off)        DDR Data Rate  1.333GT/s    frequency  667MHz

Probably there is problem in DDR frequency measurement.

Karymov, do you have any idea bout the root cause?

Have a great day,
Yiping

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[yipingwang]

Hello Chris,

Here is the SDK default RCW rcw_5g_1500mhz.bin for your reference.

RCW:

1260 0000 0000 0000 241C 0000 0000 0000

648E A0C1 C3C0 2000 DE80 0000 4000 0000

0000 0000 0000 0000 0000 0000 D003 0F07

0000 0000 0000 0000 0000 0000 0000 0000

MEM_PLL_CFG[8-9] : 01 Higher frequency reference clock.

MEM_PLL_RAT [10-14] : 10000 16:1 (async mode) 60 MHz

DDR Data Rate 1.600GT/s

You could download and install QCS tool from Processor Expert Software: QorIQ Configuratio|Freescale, then create a PBL project to assist your development.

Have a great day,
Yiping

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[Bulat]

We believe that bit mapping in the Manual is correct. Can you describe your tests and explain why you made such conclusions?