P2020 DDR initialisation problem

[Nikolay_Bala]

Hi, i am writing embedded program for p2020 board and have troubles with configuring ddr controller.

First i load and run startup program from default TLB0 4k entry at 0xFFFFF000, that configures CCSR as TLB1 entry 1 at 0xFF700000, L2 SRAM as TLB2 entry 2 at 0xFA000000. After that, program loaded at L2 SRAM initialises 1st DDR chip as TLB1 entry 3 at 0x0, size 256 megabytes, but when I try to access DDR memory board hangs.

During DDR configuration I perform these steps:

1. configuring TLB1 entry 3:

selecting TLB1 entry 3 in MAS0;

setting up valid bit and translation size 256 megabytes in MAS1;

setting up effective page number 0, write-back, non-cacheable in MAS2;

setting up real page number 0 and all permission bits in MAS3.

2. configuring CCSR DDR registers:

setting up chip select bounds from 0x000 to 0x00F (they are 12 msb's of 36-bit address);

setting up ddr memory options, such as row, column bits, timings, etc, taken from memory manufactorer datasheet;

turning on hardware calibration and waiting for complete;

enabling DDR SDRAM interface logic in DDR SDRAM control register.

3. configure local access window:

setting up base 0x0 in LAW base register

setting enabled bit, memory type DDR and size of LAW 256 megabytes.

Are this correct? Without this DDR initialisation, if I try to access configured memory window 0x00000000 - 0x0FFFFFFF rises TLB data error exception, that seems okay. But after DDR init, any access to DDR memory hangs board without any errors/exceptions. How can I find what could case a hang? Are there any way to check that  DDR controller is alive and connected by the right way?

Thanks &  Regards,

Nikolay

[Nikolay_Bala]

At last I found error - this behaviour was caused by incompatible DDR Controller and DIMM frequency modes (maximal ones).

First I set up lower frequency rates for both of them, after recalculated all appropriate timing latencies and now DDR memory turns on and works without any errors.

[francescosolito]

Good morning Nikolay.

I have a very similar problem. Could you please post the part of the code that refers to memory initialization (TLB areas, CCSR, LAWs and DDR settings), the DDR3 chip part number and the frequencies and datarates that work correctly?

Did you solved the hang problem through changing the TLB -> LAW -> CCSR order or by changing just the DDR settings?

Thank you very much.

Kind regards,

Francesco Solito

[lunminliang]

Good to know that and thanks for sharing.

[Nikolay_Bala]

Clocks and ratios, using in this board are:

SYSCLK = 80 MHz (from quartz generator)

1) platform ratio 5:1 (101)

2) e500 core 0 and 1 ratios 5:2 (101)

3) ddr controller ratio 10:1 (1010)

And due to those ratios, frequencies will be:

1) CCB clk freq = 400 MHz (SYSCLK * 5).

2) e500 clk freq = 1000 MHz (CCB clk * 2.5)

3) ddr clk freq = 800 MHz (SYSCLK * 10)

Are thouse computations correct?

After frequencies have been checked with oscilloscope, I found, that clock frequency (from DDR controller to memory chips) is 400 MHz (should be 800?), and also noticed one strange thing - if ratio values changed to synchronous mode, then clock frequency (from DDR controller to chips) become 200 MHz (should be 400, equal to CCB clock?).

[marius_grigoras]

Hi Nikolay,

As far I remember, the second step (DDR CCSR set up) must be done after the LAW set up. Please make a try.

Regards,

Marius

[Nikolay_Bala]

Marius Viorel Grigoras wrote:

Hi Nikolay,

As far I remember, the second step (DDR CCSR set up) must be done after the LAW set up. Please make a try.

Thank you, I'll try that.

Now I initializing DDR as: TLB -> CCSR -> LAW.

As you adviced I'll change it to LAW -> CCSR. Should I init TLB before, or after that?

[marius_grigoras]

In our PA board-bring-up scripts we're using next flow: TLB -> LAW -> DDR initialization using DDR memory mapped registers.

For a "nice" and proper DDR initialization please make sure for next steps:

1. deactivate the DDR controller using DDR_SDRAM_CFG register

2. make the initialization (make sure that you set up the D_INIT bit from DDR_SDRAM_CFG_2)

3. make a sleep

4. activate the DDR controller using DDR_SDRAM_CFG register

5. make another sleep

Hope it helps,

Marius

[lunminliang]

Please see below technical support comment:

1) Unsuccessful DDR controller initialization (DDR_ERR_DETECT[ACE]=1) could cause described behaviour.

2) It is recommended to use a debugger to doublecheck all MMU, LAW and DDR controller settings after initialization. Also it is posible to use attached P2020RDB-PC configuration file as a reference, modify it accordingly and test the DDR SDRAM operation by running CodeWarrior memory tests.

3) If the board is aproprietary one, it also needed to doublecheck the processor connection schematics.

[Nikolay_Bala]

Lunmin Liang wrote:

Please see below technical support comment:

1) Unsuccessful DDR controller initialization (DDR_ERR_DETECT[ACE]=1) could cause described behaviour.

2) It is recommended to use a debugger to doublecheck all MMU, LAW and DDR controller settings after initialization. Also it is posible to use attached P2020RDB-PC configuration file as a reference, modify it accordingly and test the DDR SDRAM operation by running CodeWarrior memory tests.

3) If the board is aproprietary one, it also needed to doublecheck the processor connection schematics.

Yes, DDR_ERR_DETECT[ACE] bit is setting to 1.

Could wrong controller or memory chip timings cause that?

Unfortunately I can't use jtag with this board, because of hardware bugs, so I decided to wrote my own initialization program, that turn on basic peripherals and io devices, as one of decisions of that problem.

I doublecheck the processor connection schematics, all hardware (except of jtag as I said before) correctly connected.

[lunminliang]

You wrote:

> Could wrong controller or memory chip timings cause that?

1. Yes.

Use attached p2020DS CW configuration script as a reference. The script is for 666MHz DDR data rate (333MHz DDR SDRAM clock).

[Nikolay_Bala]

Thank you, it is very helpful.

There are few lines in that file, function init_board:

  # DDR_SDRAM_MODE

  mem [CCSR 0x2118] = 0x00021421

  # DDR_SDRAM_MODE_2

  mem [CCSR 0x211C] = 0x04000000

  # DDR_SDRAM_MD_CNTL

  mem [CCSR 0x2120] = 0x00000000

Here you are using DDR_SDRAM_MODE registers to set up mode registers for 1 DIMM chip.

There are description in P2020 QorlQ Integrated Processor Reference Manual, that DDR_SDRAM_MD_CNTL can be used to set up mode register value, with CS_SEL, MD_SEL, MD_VALUE fields.

There are 4 DIMM's on my board.

Do I need DDR_SDRAM_MD_CNTL to configure them all, or it is wrong, and I have to do this with DDR_SDRAM_MODE register?

Can you explain, please, what is the difference between usage of DDR_SDRAM_MODE and DDR_SDRAM_MD_CNTL?

[lunminliang]

Do I need DDR_SDRAM_MD_CNTL to configure them all, or it is wrong, and I have to do this with DDR_SDRAM_MODE register?

Yes.

Can you explain, please, what is the difference between usage of DDR_SDRAM_MODE and DDR_SDRAM_MD_CNTL?

Please read the P2020 QorIQ Integrated Processor Reference Manual, 8.5.3 JEDEC standard DDR SDRAM interface commands, starting from ".Mode register set(for configuration)"

[hwrobel]

An ACE is a rather fundamental error on DDR initialization. If you have an ACE, working on TLBs or LAW will not fix it. ACE refers to DDR side issues only. It is possible to have a DDR interface that appears to work with an ACE, depending on settings. Rest assured that any set D_INIT must clear by itself and that ACE must remain cleared if you want to ever be able to use your DDR reliably.

An ACE can be caused by any number of things and it is hard to single out a “most common” cause.

Bad controller settings including mode register settings, bad DDRCDR values are reasons on the SW side. Check AN4039.

Bad termination/calibration resistors, violation of AN3940, or even a mismatch of strobe signals and corresponding byte lanes during a too creative PCB layout session are reasons on the HW side.

I would start with AN3940, schematics, and the layout. Then you may want to recheck all your settings based on AN4039 and the DDR vendor data sheets. Tools like the QCS may help you with settings. Make sure you download the most recent version of any docs or tools.

Hope this helps.