P1013 PCIE Inbound and Outbound configuration

[sujanathinaraya]

Hi, 

    1.   I am working on two  P1013 boards. In that each contains 3 PCIE controllers. one PCIe controller(RC) is connected with other P1013 processor PCIE controller(End point). Inbound window is configured in endpoint . Outbound window is configured in RC. Physical memory is available in endpoint which is used for data communication between two processors. Is outbound window possible in Endpoint side or vice versa?

2. I referred P1022 reference manual. In that L2 cache is used between two cores. I am using P1013 single core processor.  L2/SRAM cache configuration is not available in u-boot start.S? Is L2 cache configuration is required or not?

[TrinathK]

Hi @ufedor 

Give an example outbound configuration in EP and inbound configuration in RC for LS1046 board.

Thanks

[sujanathinaraya]

Thanks for your Reply ufedor,

 What i understood from your reply is inbound window can configure only in salve side(EP) and Outbound window can configure  only in Master side(RC). Is it correct?

[ufedor]

> inbound window can configure only in salve side(EP) and

> Outbound window can configure  only in Master side(RC).

Not correct.

RC and EP both could have Inbound and Outbound windows.

[sujanathinaraya]

1) Yes.

For EP it is required to have Command_Register[Bus_Master]=1.

Then why you asked me to configure EP as Master for Outbound configuration.

[ufedor]

> why you asked me to configure EP as Master for Outbound configuration.

How do you plan to use Outbound window without bus mastering capability???

[sujanathinaraya]

My assumption is RC can configure Master and EP means slave. Is it correct?

[ufedor]

EP could master (initiate) PCIe transactions through its Outbound Window if Command_Register[Bus_Master]=1.

[ufedor]

1) Yes.

For EP it is required to have Command_Register[Bus_Master]=1.

2) The L2 cache initialization is available in the 'cpu_init.c'