P1022 Incorrect i2c clock frequency

[rro]

We are configuring our i2c clock-frequency to be 100,000 kHz, but are measuring just about 2x that with the oscilloscope (199 in attached picture, also measuring ~189 on occasion). 

i2c@3100 {
			clock-frequency = <100000>;
};

kernel logs indicated a correct clock-frequency being set

[ 3.458027] mpc-i2c ffe03100.i2c: clock 94696 Hz (dfsrr=43 fdr=13)
[ 3.464217] mpc-i2c ffe03100.i2c: timeout 1000000 us

CCB is 533MHz

Kernel is 4.19.87

[khushbur]

Hi @rro 

Please refer p1022 reference manual section 11.4.3 I2C frequency divider register and 11.4.7 I2C digital filter sampling rate register. I2c frequency can be affected by FDR. Please refer application note AN2919 for FDR calculation.

Thanks

Khushbu  

[rro]

hi,

Yes I have consulted that section and confirmed that everything is being computed correctly, at least according to what the kernel messages say.

But as I mentioned, the reported set frequency does not match the measured frequency with the oscilloscope

[khushbur]

Hi @rro 

Can you please set clock-frequency = <400000> and measure clock. Please also share your dts file.

Thanks

Khushbu

[rro]

I need to clarify internally how I should proceed on this issue. I will follow up with more information / the results of the 400000 test.

The relevant section of the DTS has already been provided in the original post

[rro]

Hi,

None. Everything is built using a custom toolchain built using crosstool-ng for the powerpc-e500v2 architecture 

[khushbur]

Hi @rro 

Can you please share kernel version and boot logs?

Thanks

Khushbu

[rro]

Kernel version is 4.19.87

relevant logs

U-Boot 2019.07-rel_6_1_0 (Aug 01 2022 - 13:53:06 +0200)

CPU0:  P1022, Version: 1.1, (0x80e60011)
Core:  e500, Version: 5.1, (0x80211151)
Clock Configuration:
       CPU0:1066.667 MHz, CPU1:533.333 MHz,
       CCB:533.333 MHz,
       DDR:400  MHz (800 MT/s data rate) (Asynchronous), LBC:533.333 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
I2C:   ready
DRAM:  Detected UDIMM M3ST-2GSVFLPC-E
2 GiB (DDR3, 64-bit, CL=6, ECC off)
Flash: 256 MiB
L2:    256 KiB enabled
MMC:   FSL_SDHC: 0
Delay startup for 1000 ms to wait for FPGA configuration!
PCIe1: Root Complex, x1 gen1, regs @ 0xffe0a000
PCIe1: Bus 00 - 02
In:    serial
Out:   serial
Err:   serial
MA0:   00:01:bb:01:e5:29
MA1:   00:01:bb:21:e5:29
RTC:   Valid
Net:   eTSEC0, eTSEC1 [PRIME]

....

[    0.000000] Linux version 4.19.87 (gcc version 9.2.0 (crosstool-NG - rel_1_24_4)) #1 SMP PREEMPT Fri Jul 22 13:58:29 CEST 2022

....
[    3.442921] i2c /dev entries driver
[    3.446552] mpc-i2c ffe03000.i2c: clock 396825 Hz (dfsrr=32 fdr=3)
[    3.452739] mpc-i2c ffe03000.i2c: timeout 1000000 us
[    3.458027] mpc-i2c ffe03100.i2c: clock 94696 Hz (dfsrr=43 fdr=13)
[    3.464217] mpc-i2c ffe03100.i2c: timeout 1000000 us

[khushbur]

Hi @rro 

Which sdk version you are using for your setup?

Thanks

Khushbu