MMU TLB Initialization

[frankdischner]

Hello,

Is there any documentation about the 128-bit values used to initialize the TLB entries within the tcl scripts? I mean the lines that look like this:

# define   1GB TLB entry  7: 0x00000000 - 0x3FFFFFFF for DDR

cacheable

    reg ${CAM_GROUP}L2MMU_CAM7 = 0xA00000061C0800000000000000000001

I haven't found anything in the reference manuals that match these values, but it's possible that I'm not looking in the right place.

This is what I've been able to deduce so far, but I'm not sure it's correct:

First word: Some size value in the upper bits, WIMGE in the lower bits

Second word: No idea, seems to always be 1C080000

Third word: Start address

Fourth word: Same as third word, but with lowest bit set (no idea what that bit signifies)

What I'm most interested in are the WIMGE bits. Judging by the values and comments in the default scripts, it seems that these are mapped directly to the lowest bits in the first word. So in the example above, the value of 6 means that the M and G bits are set and a value of E would mean bits I, M and G are set. Is that correct? If so, is there a reason that the DRAM is marked as guarded by default?

Thanks,

-Frank

[marius_grigoras · Accepted solution]

Hi,

Please take a look at chapter 5.10.5.4 TLB Register Details from Targeting_PA_Processors.pdf manual (PA\Help\PDF). Here you'll find full details about these friendly registers.

By the way, we're using this friendly format to avoid the users struggling with the initialization of the MAS0-4 registers.

Regards,

Marius

[frankdischner]

Thanks Marius, this is exactly what I was looking for.

-Frank