JTAG Connection,failed to reset the target.

[ruihuang]

Hi,our core board are designed based on the P1020 processor,which has two DDR3 and one NOR flash. The JTAG interface has connected to the P1020 directly ,including SRESET,HRESET and TRST. But the DDR3 and NOR FLASH chips have no Power reset circuit or Reset chip.In this case,do the DDR3 and NOR FLASH reset signals have an effect on the core board Global reset? And does this unfavorable effect lead to the unsuccessful JTAG connection?

[alexander_yakov]

I do not think missing power on reset circuit on NOR flash or DDR3 chips can corrupt debugger connection to the processor core.

Please check connections around the processor - reset configuration pins, clocking, reset circuit and etc.

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