Hi,
We have designed a product using p2020 cpu referring to the design of p2020rdb-pc board.
We changed the chip of DDR to 4GB.
My ddr is 2 rank, I have modify the following codes in p1_p2_rdb_pc.h:
#define CONFIG_SYS_SDRAM_SIZE_LAW | LAW_SIZE_4G |
#define CONFIG_CHIP_SELECTS_PER_CTRL | 2 |
But I don't understand the following cods in board/freescale/p1_p2_rdb_pc/ tlb.c:
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1),
#else
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif /* P1020MBG */
#endif /* not L2 SRAM */
#endif /* RAMBOOT/SPL */
I found config_sys_init_l2_addr has been defined in p1_p2_rdb_pc.h. So did that mean there don't set tlb_entry 8 for ddr to p2020rdb-pc?
If I want to assign 4GB memory map to DDR, how should I modify the above codes in tlb.c?
Best regards,
Min Zhao
Hello Min Zhao,
Please refer the following source code from SDK 1.6, and please attach p1_p2_rdb_pc.h and tlb.c which you are using.
In addition, as we discussed previously, in u-boot, it is impossible to map the whole 4G DDR memory in MMU configuration, because u-boot is 32bit address space program(totally 4G).
Again, please learn the application note http://cache.freescale.com/files/32bit/doc/app_note/AN4064.pdf?&Parent_nodeId=&Parent_pageType=, especially the section "Utilizing 36-Bit Physical Addressing in U-Boot".
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif /* P1020MBG */
#endif /* RAMBOOT/SPL */
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#if CONFIG_SYS_L2_SIZE >= (256 << 10)
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1)
#endif
#endif
Thanks,
Yiping
I think no if CONFIG_SYS_INIT_L2_ADDR defined.
Anyone could confirm?