Have a great day,
See for example
http://www.icplus.com.tw/Data/Application%20Note/IP1001%20PCB%20layout%20guideline%20Apr%2017%20V15....
The P2041 RGMII implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If so, additional PCB delay is probably not needed.
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