P5020/P5010 Hardware Specifications/Reference Manual Specific FAQs

表示  限定  | 次の代わりに検索 

P5020/P5010 Hardware Specifications/Reference Manual Specific FAQs

P5020/P5010 Hardware Specifications/Reference Manual Specific FAQs

According to Recommended Operating Conditions for P5020 in P5020 HW Spec, GVDD = 1.35V/1.5V while XVDD = 1.5V/1.8V. What power should I use for the XVDD? 1.5V? 1.8V? According to P4080 specs, XVDD = GVDD. Does this mean that I should read XVDD = GVDD = 1.35V/1.5V?

Please refer to the P5020 Hardware spec and you will see that for 5020 XVDD!= GVDD. Hence, we recommend you to choose the XVDD input voltage based on the requirements of the device(s) that you will connect to this interface and your power consumption requirements for this block.

According to the P5020RM the bit SEC_VIO3 in HPSVSR register is set when TMP_DETECT goes low. What will happen when LP_TMP_DETECT goes low?

When LP_TMP_DETECT goes low, it should set the ET1D (External Tamper 1 Detect) bit in the LPSR (LP Status Register). LP_TMP_DETECT is enabled by first setting the ET1_EN bit of the LPTDCR (LP Tamper Detect Configuration Register). Please note that this input is disabled at reset, and must be enabled by software.

When enabled, LP_TMP_DETECT going low will cause the Zeroizable Master Key to be cleared. Depending on the value of the LPSV_CFG (LP Security Violation Configuration) field in the HPSVCR (HP Security Violation Control Register), LP_TMP_DETECT may cause the System Security Monitor State to go to fail. This will cause Critical Security Parameters (CSPs) in CAAM to be cleared.

Note that when enabled and LP_TMP_DETECT goes low, all of this will occur asynchronously, without need of the clock. On the other hand, when TMP_DETECT goes low, that is captured synchronously and therefore requires a clock.

Can you please list the power-up sequencing steps for P5020?

P5020 requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up:

1. Bring up OVDD, LVDD, BVDD, CVDD, and USB_VDD_3P3. Drive POVDD = GND.

- PORESET input must be driven asserted and held during this step

- IO_VSEL inputs must be driven during this step and held stable during normal operation.

- USB_VDD_3P3 rise time (10% to 90%) has a minimum of 350 ms.

2. Bring up VDD_PL, VDD_CA, VDD_CB, SVDD, AVDD (cores, platform, DDR, SerDes) and USB_VDD_1P0. VDD_PL and USB_VDD_1P0 must be ramped up simultaneously.

3. Bring up GVDD and XVDD.

Since USBx_VDD_1P0 and VDD_PL are both 1.0V and they have to ramp up simultaneously, would it be safe to generate both voltages from the same regulator (i.e. connected to the same voltage plane)? Or is there a specific reason to keep them separate?

USBx_VDD_1P0 and VDD_PL can be powered from the same regulator for P5020 since they are both 1.0V, but they need to be filtered per the HW spec.

If I don't intend to use the #LP_TMP_DETECT pin on my P5020 design, should I just connect it to 3.3V through a 4.7K resistor? Also, should I connect the VDD_LP pin directly to 3.3V?

P5 features low power tamper detect support signals (LP_TMP_DETECT and VDD_LP). If this feature is not to be used on P5, LP_TMP_DETECT (AE28) and VDD_LP (AD28) can be left unconnected, but should be tied to GND to reduce noise.

What is the output impedances for each of the following functional blocks of the P5020: 1) Local Bus interface utilities signals | 3.3V 2) DDR3 signal | 1.5V 3) eTSEC/10/100 signals | 2.5V 4) DUART, system control, JTAG | 3.3V 5) I2C | 3.3V 6) eSPI and SD/MMC | 3.3V?

The output impedance is 45 ohm for all but DDR. For it is 40 ohm for half strength mode and 20 ohm for full strength mode.

For P5020, are signals EC_RX_ER and EC2_RX_ER in MII mode?

Yes, EC2_RX_ER (pin AH29) and EC1_GTX_CLK125 (pin AK34) are in MII mode. EC1_TX_CLK with EC1_GTX_CLK125 acts as the primary function and EC1_TX_CLK performs the secondary mux functionality.

‎08-06-2012 11:37 AM