P1020/P1011 Clocking Specific FAQs

[#1]

Can you give detailed information about P1011/20 clock in sources - SYSCLK, DDCCLK and eTSEC_Clock_125? Do these CLOCK source in support Spread Spectrum? What about SD_REF_CLK/SD_REF_CLK#?

The spread spectrum parameters table in P1020 HW Spec is valid for SYSCLK and DDRCLK.

Spread spectrum clock is not supported for EC_GTX_CLK125 (RGMII).

For SERDES, SD_REF_CLK/SD_REF_CLK_B are designed to work with a spread spectrum clock (+0 to –0.5% spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used.

Please note that since SGMII doesn't support spread spectrum, if SGMII is used on any SERDES lane, spread spectrum should not be applied to SERDES REF Clock.