Hello @Mehta ,
that is depended on used IO library IP.
I would assume that in this case, number of output transistors is chosen based on CFG_PAD_MIIx_TX / D32_OS. Higher number of transistors = faster rise/fall time on a pad = higher dV/dt = higher noise. You may refer to this picture 2.7 I/O Cells - imagine that M1 and M2 are split on several parts and you control gate for each part by a combination logic...
You should measure different rise/fall times with different driver speed.
Best regards,
Pavel