UM10944 (SJA1105TEL) error in Clock selection Matrix: MIII4_RGMII_TX_CLK support for PLL0 missing

[GlennKessler]

In UM10944 table 79 on page 67 the clock selection matrix states allowed CLKSRC selections.
Therein a bit has been set in the wrong line:
Instead of MIII4_RMII_TX_CLK, the bit 'a' should be set in the line of MIII4_RGMII_TX_CLK.