Trying to Read/Write SCFG_EMIIOCR Register on T1024RDB

[zbowe]

Hello,

I am currently trying to read SCFG_EMIIOCR register on the T1024RDB, but when I use command md 0xfc404 it shows the contents as deadbeef. This is the address with the offset included from the reference manual. I am wondering if there is a register offset I am missing or something else wrong. Please advise. 

Zachary Bowe

[Oswalag · Accepted solution]

Hello,

This is because the  F_C000h Address is also an offset (Offset address of the CCSR register) that has a base address of FE00_0000h.

So, please try FE00_0000h + F_C000h + 404h =  0xFE0FC404.

Try it on U-boot:

=> md 0xfe0fc404

Regards.

[zbowe]

Hello,

Thanks for your reply. I tried that and was able to write to the register. I am now trying to solve a dependency issue of EC2 on EC1. EC2 requires EC1 to be connected in order to work properly. Other NXP support has suggested that setting bit 4 of the word at address 0xfe0fc404 would select EC2_GTX_CLK125 and solve my dependency issue. However, on the devboard (T1024RDB) I am getting the following output of all zeroes. This makes me skeptical that this is the source of the issue. I would greatly appreciate any advice you can give.

I expected bit 4 of the word at 0xfe0fc404 to be 1, as I am trying to select EC2_GTX_CLK125.