Targetting 56F8367 - Clock Speed and Power Consumption

[Charlie]

Hello,

My name is Charles Barnes.  I am currently writing a DSP application for the 56F8367.  We want to run it in a power save mode when the input voltage (to the system) is very low and, because of heat concerns, we also would like to limit the power consumption of the unit allround.  The critical units of my design are the ADCs, so I can never drop them out.

It seems to me that the best way to drop our power consumption down is to manipulate the OCCS to lower the clock speed.  I have the power guy asking me for a number.  I gave him the worst case number from the Current Consumption per Power Supply Pin chart in the datasheet, but he is curious as to a rough estimate of what the power consumption will be after I drop clock speed.

I have read over the datasheet, but am having a hard time determining what kind of power savings I will be getting by dropping the clock speed.  I was wondering if anyone knew of a white pages/app notes/datasheet or any other information that would help me generate a number.  Any other information you can give me about saving power would also be appreciated.

Thanks,

Charles

[william_jiang · Accepted solution]

Normally the power  is proportional to the frequency. there is an application note to address the relationship between core power consumption and the frequencies (AN2013/D). So you can get a rough number.  If you do not want to use a peripheral, please disable the clock to this peripheral by refering to

Section 6.5.9 Peripheral Clock Enable Register (SIM_PCE) of the data sheet. Hope it helps.