TJA1103 Not Generating Clock TXC

[R_S002]

Hi, I'm using TJA1103 on my custom S32K344 board.

I have configured TJA1103 in rev-RMII, and I saw this behaviour recently because I have been using the same board for the last 2 weeks, but yesterday it suddenly stopped generating the clock.

What are the important steps to perform verification of whether the TJA1103 is working or not?

[PavelL]

Hello @R_S002 ,

Please start with check hardware: supplies, RST_N, XI and XO.

Then check registers - mainly ALWAYS_ACCESSIBLE. 

Best regards,

Pavel

[R_S002]

hello @PavelL 

Checked XIN and XOUT; they are generating an accurate 25MHz Clock signal.

and RST_N is pulled up by a 47k resistor and showing 3.3V

can't access register cause without the TX clock, I can't init GMAC

[R_S002]

ALWAYS_ACCESSIBLE Register give 21 value as decimal

[PavelL]

Hello @R_S002 ,

that's a good value. Please check registers MII_BASIC_CONFIG and PHY_STATE.

Best regards,

Pavel

[R_S002]

MII_BASIC_CONFIG is also 21 as decimal
PHY_State is 3080 as decimal which means basic state is in training

[PavelL]

Hello @R_S002 ,

MII_BASIC_CONFIG 21d shows that the rev-RMII is set.

PHY_STATE is in the training, which look like no link partner connected.

How do you observed that clock is not generated? Could you measure the clock directly on the TXC pin?

Best regards,

Pavel

[R_S002]

Hello @PavelL 

I found this interesting glitch. It would be beneficial if you could input your expertise into it.

Yes, I observed the TXC clock output via DSO, probing after the series resistance of 22 ohms.

Below mentioned is the main function where I'm trying to implement the Continuous BIST Frame Generator, which I can use for generating a standardised Ethernet frame, which I can capture from Wireshark(via Media Convertor) and the 2nd S32K344 Dev board(which is running continuous reception through GMAC_ip_ReadFrame).

Now, whenever I run this code, my TJA1103 glitches and stops generating the TXC Clock, after which I have to change the loading capacitor of my crystal oscillator to generate the TXC clock again.

int main(void) {

/* Set RMII configuration for EMAC in DCM module */

IP_DCM_GPR->DCMRWF1 = (IP_DCM_GPR->DCMRWF1

& ~DCM_GPR_DCMRWF1_MAC_CONF_SEL_MASK)

| DCM_GPR_DCMRWF1_MAC_CONF_SEL(2U);

/* Initialize the microcontroller's clock system based on the provided configuration. */

Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);

/* Initialize and configure the MCU's pins for peripherals (like Ethernet). */

Siul2_Port_Ip_Init(

NUM_OF_CONFIGURED_PINS_PortContainer_0_BOARD_InitPeripherals,

g_pin_mux_InitConfigArr_PortContainer_0_BOARD_InitPeripherals);

/* Initialize the GMAC (Ethernet) peripheral with its configuration. */

Status = Gmac_Ip_Init(INST_GMAC_0, &Gmac_0_ConfigPB);

DevAssert(Status == GMAC_STATUS_SUCCESS);

Gmac_Ip_EnableMDIO(INST_GMAC_0, FALSE, 48000000U);

/* Search for the TJA110X address */

for (phy_addr = 0U; phy_addr < 32U; ++phy_addr) {

Status = Gmac_Ip_MDIORead(INST_GMAC_0, phy_addr, 2U, &register_value_0,

1U);

Status = Gmac_Ip_MDIORead(INST_GMAC_0, phy_addr, 3U, &register_value_1,

1U);

/* check for TJA110X ID */

if ((register_value_0 == 0x1B) && (register_value_1 == 0xB013)) {

break; /* found the TJA110X ID*/

}

}

/* Reset the TJA110X */

Status = Gmac_Ip_MDIOWrite(INST_GMAC_0, phy_addr, 0U, 0x8000U, 1U);

/* Wait until the TJA110X is out of reset */

do {

/* Read the value from the PHY register. This action is now in the loop's body. */

Status = Gmac_Ip_MDIORead(INST_GMAC_0, phy_addr, 0U, &register_value_0,

1U);

} while (register_value_0 & 0x8000U); /* Check the 15th bit and loop if it's 1 (TJA110X is resetting). */

// Enable all configuration access

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0x0040U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0x0040U, 0x2000, 1U);

//    Enable BIST configuration and functionality

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA800U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0xA800U, 0x4000, 1U); // Set PORT_BIST_CONTROL.CONFIG_ENABLE = 1

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0x8048U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0x8048U, 0x0800, 1U); // Set PORT_FUNC_ENABLES.BIST_ENABLE = 1

//    Configure datapath to send BIST frames to the MDI (ePHY)

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA807U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0xA807U, 0x0020, 1U);

//    Configure generator for continuous mode

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA880U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0xA880U, 0x2000, 1U);

// BIST DA {15:0}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA888U, &bist_DA_0, 1U);

// BIST DA {31:16}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA889U, &bist_DA_1, 1U);

// BIST DA {47:32}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA88AU, &bist_DA_2, 1U);

// BIST DA {15:0}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA888U, &bist_SA_0, 1U);

// BIST DA {31:16}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA889U, &bist_SA_1, 1U);

// BIST DA {47:32}

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA88AU, &bist_SA_2, 1U);

do {

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0x8102U,

&register_value_0, 1U);

} while ((0U == (register_value_0 & (1U << 2U))));

//    Start the BIST frame generator

Gmac_Ip_MDIOReadMMD(INST_GMAC_0, phy_addr, 30U, 0xA880U, &register_value_0,

1U);

Gmac_Ip_MDIOWriteMMD(INST_GMAC_0, phy_addr, 30U, 0xA807U, 0x6000, 1U);

while (1)

;

return exit_code;

}

[R_S002 · Accepted solution]

Found the issue
When writing the 0x8048U register, I accidentally only wrote the bit that I need to set, and I cleared the rest of the bits, which disabled the Ephy enable bit and MII_enable bit.
Thanks for your support