Hi Nick,
I just looked for information on recovered-clock jitter, and found nothing at all. Sorry, I can't help you there. A service request might be in order.
But I do have a concern about your proposed hardware interface. The S/PDIF signal is typically only half a volt, peak-to-peak, and the DSP will want a close to a full 3 volt swing. Also, the input pin has approximately 90k ohm internal pull-down resistor, so an AC couple through a capacitor will swing symmetrically around ground. So I think you will need both amplification and level-shifting to satisfy the 725.
In these kind of situations, I usually refer to the EVM schematic for the chip, but the EVM uses a separate S/PDIF receiver, so that doesn't help. I would file a service request, but I find that they typically just refer me to the EVM schematic. I have yet to use the S/PDIF on my DSP56721 project.
Sorry I can't be of more help.