Hi Vincent Vuarnoz,
The microcontroller uses the Interrupt Service Routine (ISR) to handle an interrupt generated by the Bridge IC. As soon as the Bridge IC generates an interrupt, the ISR checks the interrupt status of the Bridge IC to determine the interrupt sources and sets up proper event flags to inform the Main Loop program for processing the interrupt request.
Yes, it is possible that several interrupts can happen at the same time as in your example and in that case IIR will show both interrupts in the register,, however, this is very unlikely due to the interrupt prioritization capability of the device shown in table 6 of the datasheet: https://www.nxp.com/docs/en/data-sheet/SC16IS752_SC16IS762.pdf
Also take in mind that when the edge of the IOR signal (an internal signal that reads IIR register) comes close to the X1 clock that generates the interrupt, the value of the Interrupt Indication Register (IIR) might not be correct. This issue might occur if the X1 clock is very slow and the host read operation is very fast in response to the interrupt from the UART.
For your second question, clearing the interrupt line caused by first uart line, will clear the source only of the first uart line, however, since the interrupt source of the second uart line is still active, a new interrupt should appear from the second uart line.
Have a great day,
Jose
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------
