SC16IS752IBS - Interrupts

cancel
Showing results for 
Search instead for 
Did you mean: 

SC16IS752IBS - Interrupts

304 Views
vincentvuarnoz
Contributor I

Hi,

We are using the SC16IS752IBS and it's not clear from the documentation if several interrupts can happen at the same time. The IIR register shows the source of the interrupt in a prioritized bit mapping. Is it possible that, for example, an RHR interrupt (IIR[2] = 1) happens at the same time as a input pin change of state (IIR[5:4] = 11) ? Following that example the IIR register would then be IIR[5:0] = 110100.

Another question: If two uarts lines are used and both have data in the RX fifo. The Interrupt line will go active and the host application will read the first uart line. Then the host will read the second uart line. What will happen to the INT line (when will it be cleared) ? What if data come in the first uart line WHILE the host is reading from the second uart line? 

Thanks in advance !

Vincent Vuarnoz

Tags (3)
0 Kudos
3 Replies

180 Views
reyes
NXP TechSupport
NXP TechSupport

Hi Vincent Vuarnoz,

 

The microcontroller uses the Interrupt Service Routine (ISR) to handle an interrupt generated by the Bridge IC. As soon as the Bridge IC generates an interrupt, the ISR checks the interrupt status of the Bridge IC to determine the interrupt sources and sets up proper event flags to inform the Main Loop program for processing the interrupt request.

 

Yes, it is possible that several interrupts can happen at the same time as in your example and in that case IIR will show both interrupts in the register,, however, this is very unlikely due to the interrupt prioritization capability of the device shown in table 6 of the datasheet:  https://www.nxp.com/docs/en/data-sheet/SC16IS752_SC16IS762.pdf

 

Also take in mind that when the edge of the IOR signal (an internal signal that reads IIR register) comes close to the X1 clock that generates the interrupt, the value of the Interrupt Indication Register (IIR) might not be correct. This issue might occur if the X1 clock is very slow and the host read operation is very fast in response to the interrupt from the UART.

 

For your second question, clearing the interrupt line caused by first uart line, will clear the source only of the first uart line, however, since the interrupt source of the second uart line is still active, a new interrupt should appear from the second uart line.


Have a great day,
Jose

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 Kudos

180 Views
vincentvuarnoz
Contributor I

Hey Jose,

Thank you for your reply.

By "a new interrupt should appear" do you mean that there will be a transition from  LOW to HIGH to LOW again ?

Because when the line is idle, the IRQ signal is HIGH. Then the first interrupt comes in, it goes LOW, then the second comes in, it stays LOW and then the micro-controller reads from the first uart and clears the line, it goes HIGH. In that case the microcontroller cannot see that there was an interrupt concerning the second uart... Or each time it detects an edge on the IRQ signal, the microcontroller should check both uarts ?

Thanks for clarifying !

Have a great day too !

Vincent

0 Kudos

180 Views
reyes
NXP TechSupport
NXP TechSupport

Hi Vincent,

 

By "a new interrupt should appear" do you mean that there will be a transition from  LOW to HIGH to LOW again?

Correct, but only if there are interrupt source in both UART lines at the same time.

0 Kudos