SC16C752 FIFO Ready Bit

[Falki]

In our product we replaced the TI part with the NXP SC16C752 dual UART.
According to the manual, the chips should be compatible, however, I've noticed some difference.
I'm using the 64 byte FIFO with a TX level of 8 bytes on serial port B.
To check whether I'm allowed to send characters to the FIFO, I'm checking the "TX FIFO B status" bit in the "FIFO Rdy" register.

In case the FIFO gets full, the status bit is cleared.
When 8 bytes are available again in the FIFO, an interrupt is generated, IIR contains 0x03 and after reading IIR 0x01.
However, reading the "TX FIFO B status" bit in the "FIFO Rdy" register will give me a value of 0x01, meaning, there no room in the FIFO B.
Furthermore, this bit will not change until the FIFO is completely empty.
 
The behavior is not what I expected and what I interpret from reading the manual. Also the TI chip showed this status as expected.

Is there anything I'm missing?
Did anybody else notice this behavior?

[Falki]

Hi Tomas,

Sorry for the long wait, and thank you for the detailed investigation.

I see the difference, but does not explain what I see.

To summarize:
Both, TI and NPX, should clear the TX bit in case there are fewer than level spaces in the FIFO.
TI will set the bit again upon reaching the level, NPX only if the FIFO is full.

But what I see is, that NPX does NOT clear the TX bit, even when there are fewer than level spaces, but rather only on FIFO empty. Therefore, it seems not to follow /TXRDY as assumed.

Anyway, I just thought I missed something, or setting some bit in yet another register to make it work as expected.
However, it looks like there is no chance to find a solution on a such old device.
Just wondering why I'm the only one hitting this problem.

Regards,
Martin

[TomasVaverka]

Hello Martin,

This device is almost 20 years old and the datasheet does not have a very clear description of the bits in the FIFO RDY register. The engineer who designed this device is long gone. We do not have much history on this device. But from the TI's datasheet:

When bit 0 or bit 1 is set, this means that there are at least a TX trigger level number of spaces available in the TXFIFO. What this means is that the TXFIFO is not empty can be written with more data.

From the NXP datasheet, it suggests that the FIFO Ready register should work according to the DMA function of /TXRDY and /RXRDY pins. In DMA mode 1, the pin /TXRDY should work as follow:

/TXRDY pin is set when the TXFIFO is full (no spaces), and clear when there are at least a TX trigger level number of spaces available in the TXFIFO. I would expect the bits in the FIFO RDY registers reflect the of /TXRDY and /RXRDY pins. So, there is a difference in behavior between the TI and the NXP part. Unfortunately, I cannot check that with the design team. We do not have a test setup to compare the behavior between NXP and TI.

Best regards,

Tomas