S32R45 board, how to drive PCIE work?

[lihongliang]

hi, 

    We designed our own hardware board based on S32R45, Currently, pcie debugging encounters some problems, hope your help, thank you!

     S32R45 SoC has two SerDes modules (0 and 1), each of them with one PCIe controller. Now, let me address the two main issues(only target at PCIE1 below):

     1. Failed to stabilize PHY link(ssd card has been inserted)

         

     2. The internal 100MHz reference clock could not be detected by oscilloscope.

Attention:

     1. I configed pcie to RC mode.

     2. we used R45 internal 100MHz reference clock.

     3. uboot start command

         

     4. linux pcie config

         

        Otherwise, phy link nerver came up, primary cause may be 100MHz internal clock missing. From my perspective, R45 internal 100MHz(PCIE1_CLK_P/PCIE1_CLK_N) always exists after being powered on, why be gone.

      Looking forward to your reply!

[petervlna]

Hello,

Could you please share name of your company? I need it to be able ask RADAR team.

Best regards,

Peter

[lihongliang]

Thans for your reply.

Our company information is as follows, Beijing Muniu Pilot Technology Co., LTD, focus on the development and production of millimeter wave radar products.

In addition to the problems mentioned earlier, I want to emphasize this issue:

1. PCIE0/1_CLK_P/N clock pin of S32R45, whether it can be output to peripherals as a 100M reference clock(eg, PCIe SSD).If that' okay, Is there any special parameter configuration required on the software?

[alejandrolozan1]

Hello, 

Sorry for the delay! Can you provide the BSP version you are using as reference? and if possible share portions of the schematics related to the PCIe module?

Is the device detected in Uboot? Can you share the entire log too?

Best Regards,

Alejandro