S12G48 ECC Logic Test pattern for 2 bits error simulation

[sorinstan]

Hello

We currently have the following technical issue:

Processor: S12G48

Problematic: according to Safety Considerations S12G-Family Rev.0 7/2012 , Chapter 6.1 Program Flash and EEPROM, in "ECC Logic not working" paragraph, it is stated that the ECC Logic may be tested by programming a carefully choosen pattern combination. In the same paragraph we have an example of "producing" an 1 bit error. For our application we need a pattern example that covers the case of the 2 bits errors. The purpose is to test the ECC Logic during application startup with a controlled uncorrectable 2 bits error. By reading the respectively prepared pattern, we would determin if the detection of the 2 bits errors is working properly before continue execution.

Question: Is anybody able to provide such pattern combination to generate a 2 bit error in the Program Flash?

Many thanks

Sorin

[RadekS]

Hi Sorin Stan,

I obtained internal information about ECC checksum algorithm from test engineers. Unfortunately my calculated ECC values didn’t fits to description in AN4505 Safety Considerations S12G-Family.

So, I tested it on hardware and I discover that patterns in AN4505 are probably wrong because they produce double bit ECC error instead of single bit ECC error. I will report it.

Therefore I choose test&try method and I could offer combination of patters for single and double bit ECC error.

Single bit ECC error will be signalized when we write 0xFFFF FFF4 followed by 0xFFFF FF2F.

Double bit ECC error will be signalized when we write 0xFFFF FFF4 followed by 0xFFFF FFF0.

Anyway, ECC state machine test is well covered by during final test in MCU production. So, it is not necessary test whole flash by this approach. For self testing of ECC state machine once per time at one sector it is possible to use.

Additionally you can use hardware feature for testing ECC error routines (FCNFG_ FSFD, FCNFG_ FDFD). In that case, you don’t need stress flash by cumulative writes…

I hope it helps you.

Have a great day,
RadekS

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[RadekS]

Hi Sorin Stan,

I play with ECC calculator and here are other examples of patterns (tested on S12G128):

Single bit ECC error will be signalized when we write 0xFFFF DFF4 (ECC=0x20) followed by 0xFFFF FDFF (ECC=0x2E). Result value will be 0xFFFF DDF4 (ECC=0x20).

Double bit ECC error will be signalized when we write 0xFFFF FFF4 (ECC=0x44) followed by 0xFFFF FCFF (ECC=0x64). Result value will be 0xFFFF FCF4 (ECC=0x44).

I hope it helps you.

Have a great day,
RadekS

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[sorinstan]

Hi RadekS

I have finally tried your example

Double bit ECC error will be signalized when we write 0xFFFF FFF4 (ECC=0x44) followed by 0xFFFF FCFF (ECC=0x64). Result value will be 0xFFFF FCF4 (ECC=0x44).

The pattern I have used was in fact similar: 0xFFF4 0xFFFF 0xFFFF 0xFFFF (8 bytes) followed by 0xFCFF 0xFFFF 0xFFFF 0xFFFF

Even though the results in Flash are as expected namely 0xFCF4 0xFFFF 0xFFFF 0xFFFF, the DFDIF flag in FERSTAT never gets set. So the CRC double bit error is not detected (or it is not present).

Is the pattern I have used able to generate indeed a Double Bit error? Is there anything else I should consider?

Many thanks for you help and support

Sorin

[RadekS]

Hi Sorin,

Yes, it depends on bit positions in half phrase.

In your case 0xFFF4 0xFFFF will generate ECC=0x7D and 0xFCFF 0xFFFF will generate ECC=0x79. Result value in flash will be 0xFCF4 0xFFFF with ECC=0x79.

It is strange, but MCU signalize only single bit ECC error and we read from flash 0xFCF4 value. So, it means that ECC state machine didn’t fix any bit in this word even if they detected single bit fault.

I think that this is caused by fixing one bit directly in ECC checksum. ECC for 0xFCF4 0xFFFF is 0x7B. So it make sense, that by fixing second bit in ECC checksum (0->1, from 0x79 to 0x7B) ECC state machine will fix the result.

If I will test single bit ECC fault by writing 0xFFFF DFF4 (ECC=0x20) followed by 0xFFFF FDFF (ECC=0x2E), result value in flash will be 0xFFFF DDF4 (ECC=0x20). However when I will read this data, I will get 0xFFFF DFF4 and 1bit ECC error - ECC state machine fixed data by change from 0xDDF4 to 0xDFF4 (ECC for 0xFFFF DFF4 is 0x20).

I hope it helps you.

Have a great day,
RadekS

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[sorinstan]

Hi RadekS

thanks for your feedback. we will need to try one of the examples and see how it works for us. I will get back with our feedback.

Have a good one,

Sorin