Hello,
Built-in CodeWarrior Example Projects
After installing CodeWarrior for QorIQ LS Series ARMv8, the following stationery/example projects are available directly in the IDE:
Bare-Metal Project Creation (New Project Wizard)
- Open CodeWarrior IDE → File > New > ARMv8 Stationery
- Select: ARMv8 > Bare board > Hello World C Project
- Build and debug the bare-metal project
AMP Multicore Example (HelloWorld_C_AMP_Bare)
Located at: <CWInstallDir>\CW_ARMv8\ARMv8\CodeWarrior_Examples\HelloWorld_C_AMP_Bare\
This example includes:
- Bare-metal startup code (
start.S)
- Exception handlers (
exceptions.c, exceptions.S)
- Linker scripts with configurable
___DDR_ADDRESS, ___MEMORY_SIZE, ___CORE_NUMBER
- SMP/AMP multicore support
Multicore tip (LX2160A/LX2080A): To run on cores beyond Core 0 and Core 1, duplicate the LX2160A_RDB target connection and modify the Target Initialization File with the correct CORE_CONTEXT and SAP_CORE_CONTEXT for each additional core. Disable DDR/PHY re-initialization for secondary cores.
Library Projects (source available for recompilation)
Located at: {CW_ARMv8}\ARMv8\CodeWarrior_Examples\
UART_C_Static_Lib_Bare — printf support through UART port (note: this library targets LS-series UART; the LX2160A/LX2080A uses a different UART controller — see note below)
- Switch from semihosted I/O to UART by replacing
simrdimon.specs with uart.specs in linker flags
DDR Initialization
For the LX2080A, DDR initialization in a bare-metal context follows the same flow as LX2160A:
- QCVS DDRv Tool (bundled with CodeWarrior) is used to validate DDR and generate
ddr_init.c
- The generated code can be used in your bare-metal startup or as a reference for ATF-based initialization
- DDR PHY firmware (
fip_ddr.bin) must be deployed at 0x00800000 on XSPI flash
- GPP DRAM Region #1 starts at
0x0000_8000_0000; Region #1 must be included (DPAA/QMAN dependency)
Linker script DDR configuration example:
PROVIDE (___DDR_ADDRESS = 0x80000000);
PROVIDE (___MEMORY_SIZE = 0x1effffff);
PROVIDE (___CORE_NUMBER = 0);
PROVIDE (___START_RAM_ADDRESS = ___DDR_ADDRESS + ___CORE_NUMBER * ___MEMORY_SIZE);
UART on LX2080A — Important Note
The LX2080A UART controller is NOT backward compatible with the PrimeCell UART used in LS-series processors. The built-in UART_C_Static_Lib_Bare library only supports LS-series UART. For LX2080A UART output, you will need to implement your own driver based on the LX2160A Reference Manual UART register map, or reference SDK UART driver examples.
Community resources for UART on LX2160A/LX2080A:
Real-Time Edge Software (Bare-Metal Framework)
NXP's Real-Time Edge Software includes a bare-metal framework for LX2160ARDB-REV2 (compatible with LX2080A designs):
- U-Boot-based bare-metal framework for low-latency scenarios
- Includes GPIO, IPI, inter-core communication examples
- Available at: Real-Time Edge Software
Community knowledge base article: Application Development based on BareMetal framework in Real-Time Edge Software
Regards