RS485 console setup and M-core not working after linux Boot.

ajaysinh9484 · ‎12-31-2024

hello NXP community,

currently i am working on andorid_11 based application on imx8mm evk board.

so here i am developping RPMsg based multicore application. in my application

freeRTOS (M-core) side i configured UART1 as RS485 and UART4 is defult consol

for M-core. and also i configured i2c functionality.

Configuration pin :

1 ] RS485[UART1(A53)] in M-core : pin_mux.c

>>

IOMUXC_SetPinMux(IOMUXC_SAI2_RXC_UART1_RX, 0U);

IOMUXC_SetPinConfig(IOMUXC_SAI2_RXC_UART1_RX,

IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |

IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));

IOMUXC_SetPinMux(IOMUXC_SAI2_RXFS_UART1_TX, 0U);

IOMUXC_SetPinConfig(IOMUXC_SAI2_RXFS_UART1_TX,

IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |

IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));

// DSE is DriveStrength, FSEL is SlewRate

IOMUXC_SetPinMux(IOMUXC_UART3_RXD_GPIO5_IO26, 0U); // UART_C_CTS on schematic (VH1, pin 12) - CeLAN_DIRECTION_GPIO

// software I2C

IOMUXC_SetPinMux(IOMUXC_UART3_TXD_GPIO5_IO27, 0U); // UART_C_RTS on schematic (VH1, pin 7) - SCL

IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_GPIO5_IO27,

IOMUXC_SW_PAD_CTL_PAD_PE(1U) | // enable pull resistors

IOMUXC_SW_PAD_CTL_PAD_PUE(1U) | // set to pull-up resistors

IOMUXC_SW_PAD_CTL_PAD_ODE(1U) | // output is open drain

IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) | // fast slew rate

IOMUXC_SW_PAD_CTL_PAD_DSE(6U)); // drive strength

IOMUXC_SetPinMux(IOMUXC_GPIO1_IO11_GPIO1_IO11, 0U); // DSI_RST on schematic (VH1, pin 36) - SDA

IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO11_GPIO1_IO11,

IOMUXC_SW_PAD_CTL_PAD_PE(1U) | // enable pull resistors

IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | // Schmitt trigger input

IOMUXC_SW_PAD_CTL_PAD_PUE(1U) | // set to pull-up resistors

IOMUXC_SW_PAD_CTL_PAD_ODE(1U) | // output is open drain

IOMUXC_SW_PAD_CTL_PAD_FSEL(2U) | // fast slew rate

IOMUXC_SW_PAD_CTL_PAD_DSE(6U)); // drive strength

>> In linux side disabled node: in dtsi

&uart1 { /* baseboard, UART_C */

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_uart1>;

assigned-clocks = <&clk IMX8MM_CLK_UART1>;

assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;

fsl,uart-has-rtscts;

status = "disabled";

};

Now what i am doing.

Turn on board. loading firmware from U-boot :

setenv m4_boot 'ext4load mmc 2:8 0x48000000 rpmsg_lite_pingpong_rtos_linux_remote.bin;

cp.b 0x48000000 0x7e0000 0x4E58;bootaux 0x7e0000;'

saveenv

than boot M-core : run m4_boot

thr M-core is successfully running. and show print : " UART1 init SUCCESS "

>> now in Rs485 console(using minicom), set boudrate : 38400 and enable linefeed. (CF).

than trying to somthig write on terminal nothing write or shown on consol but intrrupt

working.and passing data true. probe with logic analyzer.

>> while i press ctrl + j. on terminal at that time on M-core console shown "*** NEW COMMAND IS IN ***"

but it works only one time. and than nothing.

next i turn board in linux android BOOT mode:

but here M-core console not responding or noting print visible. maybe M-core freeze or somthing.

but while run cmd : the stae is running.

Screenshot from 2024-12-31 17-15-42.png

cat /sys/class/remoteproc/remoteproc0/state

running

I kindly request the NXP community to assist me with an issue regarding the RS485 console setup and M-core not working during the Linux boot process. Additional configuration details and the main file are attached. freRTOS

Chavira · ‎01-06-2025

Hi @ajaysinh9484!

Thank you for contacting NXP Support!

For Linux release version L5.15.71-2.2.0 and later, the run prepare_mcore command must run
before the bootaux command.

After that you have to configure the rpmsg in device tree.

Best Regards!

Chavira

ajaysinh9484 · ‎01-07-2025

Hello @Chavira

Based on my recent investigation regarding the RS-485 configuration, I found the following:

M-Core Console Status:
The M-core firmware is stable; it neither freezes nor crashes while handling RS-485 communication.
RS-485 Configuration in Device Tree (DTS):
Below is the DTS configuration used for RS-485:

&uart1 { /* baseboard, UART_C */
/*pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
fsl,uart-has-rtscts;*/
/* GBO 6/24/22 status = "okay"; */
/* used for CeLAN */
status = "disabled";

};


pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x000 /* UART1_RX (202) >> RS-485 RDI */
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x000 /* UART1_TX (204) >> RS-485 RO */
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x000 /* UART1_CTS (208) >> RS-485 RE/DE */
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x000
>;
};

Key Observations:
- RS-485 communication works perfectly in U-Boot.
- However, after booting into Linux, RS-485 stops functioning, even though the M-Core remains operational.
Analysis and Suspicions:
My understanding is that the Linux partition might be attempting to access a resource already reserved for the FreeRTOS partition. This seems to conflict with the System Controller Firmware (SCFW) configuration.
Actions Already Taken:
- Disabled all three pins (UART1_RX, UART1_TX, and UART1_CTS) and the UART1 node in the Linux Device Tree.
- Additionally, I attempted to disable the entire GPIO4 bank in the Device Tree.
  Unfortunately, these measures did not resolve the issue.
Request for Assistance:
To achieve proper resource isolation between the M-Core and A-53 cores, I believe changes are required in the SCFW, ATF, and U-Boot configurations. Specifically, I need guidance on:
- System Controller Firmware (SCFW):
  Where and how should I configure the PADs and Peripheral Access Control for UART1/RS-485 to ensure M-Core exclusivity?
- ATF and U-Boot:
  Any additional configurations necessary to prevent Linux from attempting to access resources allocated to M-Core?
Could you please provide detailed steps or references for configuring resource partitioning on the EVK-MIMX8MM board to ensure proper peripheral isolation?

AND for :
u-boot=> run prepare_mcore
## Error: "prepare_mcore" not defined
u-boot=>

Thank you in advance for your support!

Best regards,

Chavira · ‎01-07-2025

Hi @ajaysinh9484!

Checking the code it looks like the UART1 is assigned to A core in ATF.

To assign the UART1 to M core you should do the next modification in imx8mm_bl31_setup.c changing the line RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W), to RDC_PDAPn(RDC_PDAP_UART1, D1R | D1W),

Also you can get based in the next community post

Best Regards!

Chavira

ajaysinh9484 · ‎01-07-2025

hi @Chavira

Steps Followed:

Modification in AFT Source Code:
- I modified the line in imx8mm_bl31_setup.c from:
- Screenshot from 2025-01-08 11-07-20.png
- recompiled successfully after making the changes.The updated binary was deployed to the device.
  Testing:
  Upon booting, I attempted to use UART-1 from the M core, but the behaviour remained unchanged. UART-1 did not function as expected.
  
  Attached video :
  
  Could you please confirm if any additional steps are required after modifying the ATF, such as changes in the U-Boot, device tree, or Linux kernel configuration? Alternatively, if there is another configuration or diagnostic step that might clarify the root cause, I am happy to provide further details.
  Thank you for your continued support. I look forward to your guidance on resolving this issue.
  Best regards,

Chavira · ‎01-08-2025

HI @ajaysinh9484!

I am able to use the UART1 without problem.

I attached the video and my u-boot environment for reference, I am using the iMX8MM-EVK.

I have compiled the boot loader with the changes mentioned in ATF and I can run the prepare_mcore command.

Try to compile using the source code allowed in NXP official repository.

M core example:

/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2017 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include "pin_mux.h"
#include "clock_config.h"
#include "board.h"
#include "fsl_uart.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
#define DEMO_UART          UART1
#define DEMO_UART_CLK_FREQ BOARD_DEBUG_UART_CLK_FREQ
#define DEMO_UART_BAUDRATE 115200U

/*******************************************************************************
 * Prototypes
 ******************************************************************************/

/*******************************************************************************
 * Variables
 ******************************************************************************/

uint8_t txbuff[]   = "Uart polling example\r\nBoard will send back received characters\r\n";
uint8_t rxbuff[20] = {0};
/*******************************************************************************
 * Code
 ******************************************************************************/
/*!
 * @brief Main function
 */
int main(void)
{
    uint8_t ch = "A";
    status_t status;
    uart_config_t config;

    /* Board specific RDC settings */
    BOARD_RdcInit();

    BOARD_InitBootPins();
    BOARD_BootClockRUN();
    BOARD_InitMemory();

    /*
     * config.baudRate_Bps = 115200U;
     * config.parityMode = kUART_ParityDisabled;
     * config.dataBitsCount = kUART_EightDataBits;
     * config.stopBitCount = kUART_OneStopBit;
     * config.txFifoWatermark = 2;
     * config.rxFifoWatermark = 1;
     * config.enableTx = false;
     * config.enableRx = false;
     */
    UART_GetDefaultConfig(&config);
    config.baudRate_Bps = DEMO_UART_BAUDRATE;
    config.enableTx     = true;
    config.enableRx     = true;

    status = UART_Init(DEMO_UART, &config, DEMO_UART_CLK_FREQ);
    if (kStatus_Success != status)
    {
        return kStatus_Fail;
    }

    while (1)
    {
        UART_WriteBlocking(DEMO_UART, &ch, 1);
    }
}

Best Regards!

Chavira

ajaysinh9484 · ‎01-09-2025

Hi @Chavira

Thank you for your response, but I believe there may be some misunderstanding regarding the issue. Let me clarify the configuration and the observed behaviour:

Configuration Summary:
- UART4 is configured as the M-core console.
- UART1 is configured for RS-485 communication in the M-core, with the following pin mappings:
  - Pin 202 (UART1 TX) connected to RS-485 RDI.
  - Pin 204 (UART1 RX) connected to RS-485 RO.
  - Pin 208 (UART3 RXD) connected to RS-485 RE/DE for direction control.
Behavior Observed:
- The communication between RS-485 and the M-core console works correctly when the application runs in U-Boot.
- However, after booting into Linux, the RS-485 communication stops working.
Attempted Solution Based on Your Suggestion:
- I modified the ATF source as follows:
  
  RDC_PDAPn(RDC_PDAP_UART1, D0R | D0W)
  to
  RDC_PDAPn(RDC_PDAP_UART1, D1R | D1W)
- Despite making this change, the issue persists, and RS-485 communication does not function in Linux.
  
  I would appreciate your guidance on further steps to resolve this issue, especially if there are any other areas in the ATF, U-Boot, or Linux configurations that might need adjustments.
  Looking forward to your feedback.
  Best regards,

Chavira · ‎01-09-2025

Hi @ajaysinh9484!

I understand the problem, the UART1 is not working after the linux is booting.

As you see in the video that I sent after the configurations that I made the UART1 is working after Linux boot.

I can't connect any peripheral or RS485 module to my board because is the UART for the BT module but as we can see the UART all the time.

You have to note that the modification sin ATF should be in line 113 and line 66.