Problem at setting FTM0 Clock source to SPLL DIV1 CLK using Kinetis MKE18F512

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Problem at setting FTM0 Clock source to SPLL DIV1 CLK using Kinetis MKE18F512

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JohnEE
Contributor I

Hello 

I am using fast IRC clock configuration to get 180Mhz clock connected to the FTM0 clock source.

JohnEE_0-1604495651404.png

 

JohnEE_1-1604495716322.png

 

but when starting FTM0 by  FTM0 Clock:

FTM_StartTimer(IFTM_PERIPHERAL, kFTM_FixedClock);

the timer dose not startup.

when starting FTM0 by  System Clock:

FTM_StartTimer(IFTM_PERIPHERAL, kFTM_SystemClock);

the timer  starts with no problem.

 

I need to run FTM0 by FTM0 180Mhz clock derived from the SPLL.

what could the problem be ? 

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1 Reply

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diego_charles
NXP TechSupport
NXP TechSupport

Hi @JohnEE

 

I hope you are doing well during quarantine times.


According to the KE1xx Reference Manual  section 41.1.2 FTM Clocking Information  ,the fixed clock frequency shall not exceed 1/2 of the FTM system clock frequency.

ftm_clock.JPG

Apparently, in your configuration, the fixed clock is greater than the FTM system clock. So, this seems to be the root of the issue.

On the other hand the FTM sysclock is not able to reach  180 MHz frequency neither. Since  the maximum frequency of SYS_CLK (from where FTM sysclok is derived) is 168 MHz   Further details in section  18.3Clock definitions of the RM

I  hope this helps,

If you have any comments ,please,  let me know.

Regards,

Diego.