Hi,
Anyone has information for the below parameters for chip SJA1105S.
We are referring to user manual UM11040.
- It defines the order of the scheduler predecessors.
This value shows only the relative ordering of the elements.
The highest value has the highest priority and gaps are allowed.
- It is a reference to FIFO which predecessor to Port Shaper.
We are not able to map the above configuration parameter related to chipset SJA1105S.
If any has information/suggestion for above will great help for us.
Thanks and Regards,
Mahendra
The parameter identifiers you mentioned are neither defined nor used
in any NXP documentation related to SJA1105 switch family, including
UM11040. Based on the brief descriptions you provided, with a few exceptions,
the is no one-to-one mapping between them and anything that can be
configured inside SJA1105S. For Port Ingress Virtual lan Modification
and Port Traffic Class Assignment, you can look at UM11040 Sections
5.2.5 and 5.2.3 on how VLAN IDs and priorities are assigned and
managed. For the rest, as has already been said, there are no direct
analogues. If they were taken from an applicable industry standard
specification, please update the thread with the title of the
document that defines them, I can check if we have any compliance
recommendations. Otherwise, you have to study available SJA1105S
documentation, namely UM11040 and DS420710, to understand the device
operation logic, and analyze how your requirements can be implemented,
if at all.
Regards,
Platon