PTN36043 DE/OS/EQ setting

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

PTN36043 DE/OS/EQ setting

Jump to solution
1,653 Views
jackylu
Contributor II

Dear Sir,

Good day,

For my application,

PTN36043 very close  with Processor Qualcomm SDX20.

Any comment for DE/OS/EQ setting in Processor side?

Thanks.

0 Kudos
Reply
1 Solution
1,489 Views
guoweisun
NXP TechSupport
NXP TechSupport

Hi,

By default, using the open (default) settings should work. (CHx_SETx = OPEN)

But for the first build, I would suggest to still have the pull up and pull down resistor footprints in place on the setting pins, just in case the OPEN settings are not optimum.

 

If this your new design you can consider about PTN36043A part, it will be more USB-C  compliant.

The difference between the PTN36043 and PTN36043A is that

  • In PTN36043, the unused (or un-selected) channels SSTX and SSRX are tie to low ohmic
  • In PTN36043A, the unused (or un-selected) channels SSTX and SSRX are tie to high ohmic

 

The reason is to be comply with Type-Cs safe state requirement. 

 

 

View solution in original post

1 Reply
1,490 Views
guoweisun
NXP TechSupport
NXP TechSupport

Hi,

By default, using the open (default) settings should work. (CHx_SETx = OPEN)

But for the first build, I would suggest to still have the pull up and pull down resistor footprints in place on the setting pins, just in case the OPEN settings are not optimum.

 

If this your new design you can consider about PTN36043A part, it will be more USB-C  compliant.

The difference between the PTN36043 and PTN36043A is that

  • In PTN36043, the unused (or un-selected) channels SSTX and SSRX are tie to low ohmic
  • In PTN36043A, the unused (or un-selected) channels SSTX and SSRX are tie to high ohmic

 

The reason is to be comply with Type-Cs safe state requirement.