Hi,
There is no exact timing sequence specified. If VDD_I2C is powered first in your design, ensure that VDD_P ramps up promptly and reaches the POR threshold before any I²C communication is attempted. Note that the POR reset delay time is approximately 1 µs after VDD_P crosses the threshold. So to ensure reliable operation, allow a short delay (e.g. a few microseconds) after VDD_P is stable before initiating I²C transactions.
BRs, Tomas