Hi Tom,
Thanks for the reply...
I can't find any reference to an "MPC8757" part. Did you mean something else, or are you quoting the part number of this development board that uses the MPC8541 and MPC8555 chips?
http://act-technico.industrialpartner.com/single-board-computers/sbc-mezzanine/powerpc/mpc8757.htm
I quoted the actual part number on one of our products. However, it looks like the the one you mention above.
It appears that the memory management registers BRx and ORx are defined in the datasheet in a bit reversed fashion.
Why would you assume that?
It is the only way that the source code makes sense. The 32 bit word 0xFF800801 I think translates to LSB>801001FF<MSB when mapped to the datasheet. I say this because if the V (bit 31) is set it's neighbors (bits 26 to 30) should be zero. I'm trying to clarify if this is correct. To put it another way. If you print out one of the bit field figures in the datasheet and fill in your designs requirements, the constant you use in your source code will (I think) be the mirror image. It is therefore prone to errors too. The datasheet is correct but could have been laid out it a software engineer friendly way
// BR0: 0xFF800801
lis r4, 0xFF80
ori r4, r4, 0x0801
stw r4, 0x100(r3) // BR0
Either they've kept the convention that Bit0 is the LSB and Bit31 the MSB and drawn them in a strange left-to-right LSB-to-MSB order, or they are in their usual MSB-to-LSB order, but numbered with the LSB as 31 and the MSB as 0. If you read enough of the Reference Manual (and sample code) you'll find eventually the latter is the only interpretation that makes sense.
Bit 0 is the LSB and bit 31 is the MSB by definition but I agree thay have drawn them in a strange left-to-right order. So I think it is the former but I'm looking for clarification.
Why? IBM numbered their bits this way in the 1950's and since they designed the "Power" architecture, all the Power chips have this convention. Here's a possible starting point for this:
http://upload.wikimedia.org/wikipedia/commons/6/6a/IBM360-65-1.corestore.jpg
Freescale don't mention this in any of the data sheets. It is something you JUST HAVE TO KNOW. Had you been reading every single data sheet since they started making these chips back in the early 1990 or so, and read the original IBM documents, this may be mentioned in that "chain" somewhere, but I've been reading them for nearly that long and I've never found where this is stated. I've found sentences in various documents stating that this sort of thing is defined in another specific document, but reading that one finds that they don't. I don't think anyone at Freescale has tried to learn about these chips using their documents "from scratch", because this little "bear trap" catches a lot of people. It got me when I worked on the MPC860 a long time ago.
I haven't read all the datasheets or found a statement that explains the format.
I've addressed this before in this forum. You might like to read through some of the documents referenced in the following:
https://community.freescale.com/message/93786#93786
https://community.freescale.com/message/84050#84050
Tom
Cheers
Peter.
Hi Tom,
I do appreciate the reply and feel that some of it is due to semantics. I agree there is a difference between bit numbering and what is MSB and LSB. I suspect that IBM's explanation of microprocessor arithmetic is an interesting read using their convention! Bit numbering when it relates to setting/resetting peripheral registers is a different issue. It's a pity they aren't aligned for consistency. However, if they got there first then sobeit.
>Yes, but why reverse the writing order, just to put Bit31 on the left?
Because writing software and spotting bugs is hard enough as it is. It's not so bad to just set/reset registers but you may need to read and mask etc.
Q/ What is the value of the MSB? 
0x80000000
Cheers
Peter.
> Q/ What is the value of the MSB?
> 0x80000000
For all "normal" CPUs, the "value of a bit" is "2^N" where "N" is the classic bit number.
For these CPUs, the value of a bit using their bit numbering is:
8 bit values: 2^(8-1-N)
15 bit values: 2^(16-1-N)
32 bit values: 2^(32-1-N)
64 bit values" 2^(64-1-N)
M bit values: 2^(M-1-N)
Whoever put the labels on the switches on the first IBM mainframe control panel didn't consider this. The DG Nove did the same thing with Addresses A0-A15. Then they made an 18-bit-address model. They called the two new higher-order bits "XA0" and "XA1". Oops! Better than "A-2" and "A-1" I guess.
So if you want to do the equivalent of "2<<N") to define a bit using the IBM definitions you'll have to have different ones for all the different widths. Or ignore the bit number completely and just use masks. If you want to use definitions like (1 << bit) then make sure you put comments EVERYWHERE stating what the book says and why you're using the opposite convention.
Try to stay away from the assembly code. This is the most overly complex "RISC" CPU I've ever seen. Consider RLWIMI (almost every line of C code turns into one of these), try to understand what "@ha" means in "LIS, "NNN@ha". This is so complex it has to then have "simplified mnemonics", and there are 34 PAGES! of them in the manual! Then some joker added the "Old McDonald" "EIEIO" instruction. Most CPUs have SUPERVISOR and USER modes. The early documentation designates these as SUPERVISOR and PROBLEM modes (meaning "the user is the real problem").
Tom
