MPC 8349 interfaced with 32/64 bits DDR2 bus width

[dorian_chambon]

Hi,

For my project, I use MPC8349 processor. I would like to set DDR memory controller parameters.

The DDR2 bus width shall be configurable in 32 bits mode or in 64 bits mode without HW modification. In 64 bits mode, 5 DDR2 chips are used (4 chips + 1 ECC) in 32 bits mode 3 DDR2 chips are used (2 DDR2 chips + 1 ECC) but other chips unused still connected.

- Does everyone have a return of experience ?

- What hardware precautions should we take in case of DDR2 chips connected to processor but unused ?

- How the processor MPC8349 deals with 32 bits or 64 bits bus width (internal mask ?, other method ?...) ?

-It is necessary to disable DDR2 clocks for chips unused in 32 bits mode ?

Sincerely,
Dorian.

[ufedor]

> - What hardware precautions should we take in case of DDR2 chips connected to processor but unused ?

No special precautions are needed.

> - How the processor MPC8349 deals with 32 bits or 64 bits bus width (internal mask ?, other method ?...) ?

The question is not clear.

> -It is necessary to disable DDR2 clocks for chips unused in 32 bits mode ?

It is not strictly required, but disabling the clocks will lower power consumption.

[dorian_chambon]

Hello,

thanks for your answer.

We use MT47H64M16 DDR2 chips from MICRON on a MPC8349 processor from NXP in the following configuration:

Four memory chips are connected on the 64-bit processor bus and all control signals are common to the four chips except the clocks MCK and the byte enables that are individual.

Usually the processor DDR2 controller is configured in 64-bit mode.                

But in some cases, the processor bus is configured in 32-bit mode by the boot (need of software retro compatibility with previous designs) while the four chips are still present on the bus.

In this 32-bit configuration: After power up, the two unused DDR2 chip will never see any clock edges because in 32-bit mode the clocks of these two chips are driven to a constant level.

In particular the DDR2 initialization sequence made by the processor will not be seen by the two unused chips because of the lack of clock.

Questions:

- In 32-bit configuration, DDR2 bus is configured in 32-bit mode (through SDRAM_CFG[MEM_EN] register), DDR2 unused clocks are disabled (through MCKENR register) all others DDR2 registers had the same configuration in 32-bit or 64-bit mode :

CS0_BNDS-Chip select 0 memory bounds

CS1_BNDS-Chip select 0 memory bounds

CS2_BNDS-Chip select 0 memory bounds

CS3_BNDS-Chip select 0 memory bounds

CS0_CONFIG-Chip select 0 configuration

CS1_CONFIG-Chip select 1 configuration

CS2_CONFIG-Chip select 2 configuration

CS3_CONFIG-Chip select 3 configuration

TIMING_CFG_3-DDR SDRAM timing configuration 3

TIMING_CFG_0-DDR SDRAM timing configuration 0

TIMING_CFG_1-DDR SDRAM timing configuration 1

TIMING_CFG_2-DDR SDRAM timing configuration 2

DDR_SDRAM_CFG_2 DDR SDRAM control configuration 2

DDR_SDRAM_MODE- DDR SDRAM mode configuration

DDR_SDRAM_MODE_2- DDR SDRAM mode configuration 2

DDR_SDRAM_MD_CNTL- DDR SDRAM mode control

DDR_SDRAM_INTERVAL- DDR SDRAM interval configuration

DDR_DATA_INIT- DDR SDRAM data initialization

DDR_SDRAM_CLK_CNTL- DDR SDRAM clock control

DDR_INIT_ADDR- DDR SDRAM  training initialization address

DDRCDR. Hardware DDR driver calibration is disabled

ERR_INT_EN – Memory Error Interrupt Enable

but are there any others special register to configure in case of chips physically connected but unused to DDR2 bus ?

- In 32-bit configuration, unused data DDR2 processor pins are in high-impedance ?

Sincerely,

Dorian.

[ufedor]

> but are there any others special register to configure in case of chips physically connected but unused to DDR2 bus ?

No such special registers.

> - In 32-bit configuration, unused data DDR2 processor pins are in high-impedance ?

The unused DDR interface signals are still driven in this case.