MC33771B TPL communication error with S32K

[sunghou-kim]

Hello, NXP!

I have some problems with TPL communication between MC33771B(2ea)  and MCU(S32K144) ( with MC33664).

my configuration of SPIs for interfacing MC33664's like below

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Master SPI Tx: 2Mbps / 40bits/frame / PCS : active low / Second Edge / MBS / Interrupt type

Slave SPI Rx : 40bits/frame / PCS : active low / Second Edge / MBS / Interrupt type

Core Clock 80MHz

Initial Fault Status( no change afterwards )

CID1(1st daisy chain) COM_STATUS error count 2 / FAULT1 0x0040 FAULT2 0x0000 FAULT3 0x0000

CID2(2nd daisy chain) COM_STATUS error count 2 / FAULT1 0x0040 FAULT2 0x0000 FAULT3 0x0000

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I am using NXP's BCC driver.

I'm trying to read/write registers about 20 times each, every 200ms.

But sporadically receive CRC(many)/TagID(few)/RC(few) mismatch errors. (average 1 error per 2 minutes )

At which point I should look into first to resolve this issue ?

Many thanks for your support in advance.

Sungho

[Jakub_R · Accepted solution]

Hello Sungho,

the first think I would look at is the physical interface - e.g. SPI lines, TPL lines, contacts etc. Also it would be helpful to monitor SPI/TPL lines with logic analyzer. If everything is correct, then the code you are using should be checked.

Regards,

Jakub

[sunghou-kim]

Hi, thank you for your reply.

Me Resolved this issue by increasing priority of interrupt(SPI Slave/TPL).

Somehow losing synchronous read timing when there exist competitions with other ISRs(same priorities) especially in a burst read event (eg. 31 bytes raw value access)

Thanks,

See you