Linux boot issue for custom board based on LS2160ardb on LSDK 20.04

[Conard]

Hi,

I met some issues when I try to boot up LS2160 board, it prints following log repeatly.

[ 11.361770] 007: mdio_bus 0x0000000008b96000: Error while reading PHY4 reg at 7.0
[ 11.361871] 007: mdio_bus 0x0000000008b96000: Error while reading PHY4 reg at 7.1
[ 11.361967] 007: mdio_bus 0x0000000008b96000: Error while reading PHY4 reg at 7.19
[ 11.362064] 007: mdio_bus 0x0000000008b96000: Error while reading PHY4 reg at 7.33

I can change the uboot image and login tiny Linux, but when I keep boot up to Linux, it prints these logs.

I am sure that my uboot image is correct, it works all well in another LS2160 board.

The boot up log is in the attachment.

Please let me know what should be done to resolve this issue.

Thanks!

Conard

[yipingwang]

In u-boot source code board/freescale/lx2160a/eth_lx2160ardb.c, have you modified the following PHY addresses configuration according to your custom board?

switch (srds_s1) {
case 19:
wriop_set_phy_address(WRIOP1_DPMAC2, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
AQR107_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
AQR107_PHY_ADDR2);
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
INPHI_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
INPHI_PHY_ADDR1);
}
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
RGMII_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
RGMII_PHY_ADDR2);
break;

case 18:
wriop_set_phy_address(WRIOP1_DPMAC7, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC8, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC9, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC10, 0,
CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
AQR107_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
AQR107_PHY_ADDR2);
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
INPHI_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
INPHI_PHY_ADDR1);
}
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
RGMII_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
RGMII_PHY_ADDR2);
break;