LS1043ACE9QQB : Layerscape Reset implementation

[Sandra1405]

Hi NXP Team,

We are currently using Layerscape processor LS1043A and PMIC MC33PF8200A0ES for our automotive project. We have a reference design which uses CPLD for implementing processor reset. But we are not using CPLD in our design. Kindly help us with the queries below.

1. Can we use PGOOD or RESETBMCU pin from PMIC to control the reset of LS1043A as shown in the figure below. (Attached)

Sandra1405_1-1685907693067.png

2. Do NXP have reference designs for Layerscape processor LS1043A which does not use CPLD, so that we can refer the reset implementation?

3. For PMIC MC33PF8200A0ES, can we initiate the power on sequence automatically by connecting PWRON pin directly to VIN as mentioned in the datasheet of PMIC?  (Page No:42, Section:14.9.1)

4. Can we connect RESET_REQ_B of LS1043A to WDI pin of PMIC to implement the watchdog timer through PMIC? Does the implementation below work?

Sandra1405_3-1685908358941.png

Awaiting your response...

Thanks

Sandra

[Sandra1405]

Thank you for the reply...

Have some more queries that need support, kindly help.

To control the reset logic of LS1043A processor, we are planning to use a time-based sequencer to assert the PORSET_N signal during power-on.

• Do you foresee any issues with this implementation?
• Are there any use cases where this implementation will not work?
• For which use case do we need to assert the PORESET_N signal other than normal operation?
• We would like to know the minimum & maximum duration for which the PORSET_N signal needs to be asserted to have a reliable power on sequence.

Sandra1405_0-1686641114648.png

• What does the below statement mean? Where does the common on-chip reside?

Sandra1405_1-1686641114676.png

2.. Watchdog Implementation: For a HW-based watchdog implementation, the PMIC MC33PF8200A0ES has a WDI input. Do you have any HW recommendation or reference design available for mapping the watchdog reset from SOC to the PMIC implementation.

On a watchdog event, which reset output from the SoC will be asserted RESET_REQ_B or HRESET_B?

Sandra1405_2-1686641114733.png

Sandra1405_3-1686641114763.png

Thanks,

Awaiting your response ASAP

[yipingwang]

To control the reset logic of LS1043A processor, we are planning to use a time-based sequencer to assert the PORSET_N signal during power-on.

Do you foresee any issues with this implementation?

- If you want to use a time-based sequencer to assert the PORSET_N signal during power-on, please ensure that the timing requirements from the datasheet match.

Are there any use cases where this implementation will not work?

- Only if timing requirements did not match.

For which use case do we need to assert the PORESET_N signal other than normal operation?

- Other than for normal operation, PORESET_N signal will be asserted during error cases.

We would like to know the minimum & maximum duration for which the PORSET_N signal needs to be asserted to have a reliable power on sequence.

- The minimum duration for which PORSET_N should be asserted is 1 ms, and it is important to ensure that all supplies are at their stable values during that time. Please go through LS1043A data sheet for timing requirements.

Where does the common on-chip reside?

- What is your exact requirement here?


Watchdog Implementation: For a HW-based watchdog implementation, the PMIC MC33PF8200A0ES has a WDI input. Do you have any HW recommendation or reference design available for mapping the watchdog reset from SOC to the PMIC implementation.

- This is your own customer implementation. We don’t have any reference design for this.

On a watchdog event, which reset output from the SoC will be asserted RESET_REQ_B or HRESET_B?

- RESET_REQ_B.

[D4Davis]

Thanks for the update yipingwang!

For which use case do we need to assert the PORESET_N signal other than normal operation?

- Other than for normal operation, PORESET_N signal will be asserted during error cases.
Kindly enlighten us on which error cases we need to assert PORSET_N, so that we can implement the logic accordingly.

We would like to know the minimum & maximum duration for which the PORSET_N signal needs to be asserted to have a reliable power on sequence.

- The minimum duration for which PORSET_N should be asserted is 1 ms, and it is important to ensure that all supplies are at their stable values during that time. Please go through LS1043A data sheet for timing requirements.

[From the datasheet also we found the 1ms value, this seems to be the min duration, our understanding is that the PORSET_N needs to be asserted till the power supply and clocks needs to be stable, kindly let us know there is any max duration requirement for the PORSET_N assertion.]

Where does the common on-chip reside?

- What is your exact requirement here?

We saw this note in the reference manual and did not understand this fully, that was the reason why we raised this query.

D4Davis_0-1687196731181.png

Thanks!

BR,

Davis

[yipingwang]

I am discussing with the AE team, will provide more update later.

[D4Davis]

Thanks for the update, awaiting your response!

BR,

Davis

[yipingwang]

Q. Kindly enlighten us on which error cases we need to assert PORSET_N, so that we can implement the logic accordingly.
- There is a signal called RESET_REQ_B that can be connected to PORESET_B. Whenever RESET_REQ_B is asserted, it will also assert the PORESET_B signal. Please go through LS1046ARM- Reset Request Status Register (DCFG_CCSR_RSTRQSR1), this register contains status bit to record the reasons for RESET_REQ_B assertion.

Q. From the datasheet also we found the 1ms value, this seems to be the min duration, our understanding is that the PORSET_N needs to be asserted till the power supply and clocks needs to be stable, kindly let us know there is any max duration requirement for the PORSET_N assertion.
- There is no max duration, but all supplies must be at their stable values within 400 ms.

Q. Where does the common on-chip reside?
- According to this note COP reside inside the SoC. Please give us some information about your use-case so that we can

What is your specific use case? We will be able to provide better advice if we have more information.

[yipingwang]

we shall implement in such a way that the PORESET is inverted after 400mS.

- Please refer Data sheet - Section 3.9 RESET initialization for RESET Initialization timing specifications.

Wanted to know if we need to have an interlock kind of logic for the JTAG as well when we implement the reset logic.

- Please refer the Design Checklist document - AN5012 - Section 5.28.1 (Fig 18. JTAG interface connections).

[D4Davis]

Q. Kindly enlighten us on which error cases we need to assert PORSET_N, so that we can implement the logic accordingly.
- There is a signal called RESET_REQ_B that can be connected to PORESET_B. Whenever RESET_REQ_B is asserted, it will also assert the PORESET_B signal. Please go through LS1046ARM- Reset Request Status Register (DCFG_CCSR_RSTRQSR1), this register contains status bit to record the reasons for RESET_REQ_B assertion. [Noted, we shall review and get back to you]

Q. From the datasheet also we found the 1ms value, this seems to be the min duration, our understanding is that the PORSET_N needs to be asserted till the power supply and clocks needs to be stable, kindly let us know there is any max duration requirement for the PORSET_N assertion.
- There is no max duration, but all supplies must be at their stable values within 400 ms.[Noted, we shall implement in such a way that the PORESET is inverted after 400mS]

Q. Where does the common on-chip reside?
- According to this note COP reside inside the SoC. Please give us some information about your use-case so that we can
[Wanted to know if we need to have an interlock kind of logic for the JTAG as well when we implement the reset logic]
What is your specific use case? We will be able to provide better advice if we have more information.

[yipingwang]

1. Can we use PGOOD or RESETBMCU pin from PMIC to control the reset of LS1043A as shown in the figure.

- If PGOOD is used as a GPIO, it can also be set high as part of the power up sequence in order to allow sequencing of any external supply/device controlled by the PGOOD pin.
Yes, PGOOD or RESETBMCU pin from PMIC can be used to control the reset of LS1043A. But timing requirements needs to be matched.

2. Do NXP have reference designs for Layerscape processor LS1043A which does not use CPLD, so that we can refer the reset implementation?

- https://www.nxp.com/design/designs/ls1043a-residential-gateway-reference-design:LS1043A-RGW

3. For PMIC MC33PF8200A0ES, can we initiate the power on sequence automatically by connecting PWRON pin directly to VIN as mentioned in the datasheet of PMIC? (Page No:42, Section:14.9.1)

- As per the datasheet, you are correct. Customer can able to provide the Power On event by connecting to VSNVS or VIN with an external resistor 100kohms.


4. Can we connect RESET_REQ_B of LS1043A to WDI pin of PMIC to implement the watchdog timer through PMIC?

If your intention is to power cycle the PMIC with RESET_REQ_B generated by the watchdog timer of LS1043A, then yes, it will work. However, there are other reasons when RESET_REQ_B will be asserted, leading to a power cycle of the PMIC. For example, we can also generate RESET_REQ_B by writing to the DCFG_CCSR_RSTCR[RESET_REQ] register.