LS1028A-FlexSPI-FPGA

[Andy_0b11011]

Hello everyone, I have a board that uses LS1028A and has two flash drives (A1, A2) and one FPGA (B2) mounted under the FlexSPI module. Two of the flash drives are working properly, but there are issues with the use of the FPGA.
I would like to inquire whether the FlexSPI of LS1028A supports FPGA devices, as I found in the official user manual that the FlexSPI chapter mainly covers Flash related content.
In addition, I have initially achieved communication with FPGA through FlexSPI, but its operating frequency can only be 50MHz (the frequency I set is 25MHz), and it may occasionally fail to capture SCLK signals.
The two Flash chips mounted on FlexSPI are set to a frequency of 50MHz, but the actual frequency calculated from the waveform captured by the oscilloscope is 100MHz. However, the 3-bit division coefficient (0x3) stored in the register is not incorrect (200/4=50).
What is the normal operating frequency range of the FlexSPI controller? Why is the theoretically calculated frequency inconsistent with the actual frequency captured by the oscilloscope?
If there is a demo of LS1028A-FlexSPI mounting FPGA, please send it to me
Looking forward to your answers, thank you very much!

[Oswalag]

Hello,

There isn't any demo available but LS1028A supports FlexSPI-FPGA devices, for the FlexSPI frequency you can review the AN12028 - QorIQ LS1028A Design Checklist, Table 52. FlexSPI interface frequency calculations.

[Andy_0b11011]

Thank your for replying.

There are still some bemusement. 

I don't konw how CGA_PLL and Platform PLL define the clk for FlexSPI.

The RCW[SYS_PLL_RAT] = 0b100(4:1).According to the figs above,dose it mean the clk for FlexSPI is 200MHz?

I checked the register,MCR0[SERCLKDIV]=111(FPGA used)/100(flash used).

But,the Signal captured through an oscilloscope indicated the frequency of FPGA is 50Mhz and flash is 100MHz.They are different form theoretical values.It seems like the clk for FlexSPI is 400MHz.I don't konw why.

[Oswalag]

In the RM - 18.2.3 Operation Modes
This section provides information about the modes FlexSPI could be used. Each mode has different clk configuration, at the end A_SCLK  and B_SCLK are the signals to provide the clk to the connected devices. 

Are you sure the values are MCR0[SERCLKDIV]=111(FPGA used)/100(flash used)? it looks like for flash it should be 011b - Divided by 4

[Andy_0b11011]

sorry to bother again. II reread the design file you gave me.

According to the design document you provided, is the frequency source for the FlexSPI CGA_PLL2 / 3? (I checked the values of the relevant configuration words and they are 12 and 7)

However, in section 4.8.9 of the LS1028A chip manual there is a Figure 7 which shows that the clock source for FlexSPI is Platform PLL / 2.

Which is correct, CGA_PLL2 / 3 or Platform PLL / 2?

Or is one of them the FlexSPI's own operating frequency and the other is the frequency used to divide the frequency for use by the mounted device?

Like I mentioned before, on my device tree and software architecture, the FlexSPI frequency is configured as Platform PLL / 2, but the actual frequency measured with an oscilloscope is twice as high, and actually looks like it's being divided from CGA_PLL2 / 3 for conduction to the device.

Please help with my confusion, thank you very much!

[Andy_0b11011]

I am sure the value of MCR0[SERCLKDIV] is 111(for FPGA，divided by 8)，cause I add some debug msg print in the transfer process.