Fast ethernet controller

[gri]

Hello,
I'm searching for a application note for the FEC, it should containt a schematic how to connect the cpu with ethernet connector and some sample code.

Regards

[laurentiu]

Hi,

Regarding FEC module for MPC5553 I have some problems with DMA and FIFO Controller. After a write to TDAR a frame is transmitted correctly, but after I set up another transmit frame and write to TDAR no frame is transmitted. It seems that DMA and the RISC Controller doesn't read the following buffer descriptors. Do you have a hint for this?

Thanks

[laurentiu]

I fount out the solution to the problem I had few days ago. A detailed explanation of this issue and a workaround for it can be found in Errata 2049 in the attached file.

MPC5553rev0E2.pdf

Message Edited by t.dowe on 2009-10-20 01:15 PM

[RickN]

See attached EVB schematics.

Cheers,

  Rick

mpc5553evb_sch_e.pdf

Message Edited by t.dowe on 2009-10-20 01:05 PM

[gri]

Thanks for the schematics. In the datasheet I've seen that the pins for the FEC are only available in the 416 pin BGA. This BGA is a bit to large, I want to use the 324 pin BGA or even the smaller 208 pin BGA. Is it possible to route the FEC pins to other GPIO pins using the crossbar?

Regards

[RickN]

Hi,

  Sorry, but you need to have the package with the FEC pinned out.

- Rick

[gri]

The FEC shares pins with the data bus, is it possible to use the fec and the ebi for memory in the same time?

[gri]

Hello,
where is pin 7 of the DP83848, PWR_DWN, connected. I'm unable to search insinde the pdf.

Regards

[gri]

For the MPC5553. At the beginning a schematic is engough.

Regards

[RickN]

Which MPU?