74HCT74PW - On power up, What is the default STATE of pin Q

[jeevaaraamsethu]

Part #: 74HCT74PW
Function: D-type ?ip-?op
Description: Dual D-type ?ip-?op with set and reset; positive-edge trigger;  TTL-enabled

Query:
On power up, what is the STATE of pin Q (When CP = 0)?

My expected output will be HIGH, only when the SD=HIGH, RD=HIGH and also CP is in positive rising edge. But, I’m getting output pin-5 (1Q) as HIGH, when the CP is in low state.

[jeevaaraamsethu]

Waveforms (Refer attachment: NXP-74HCT74PW-Waveforms.pdf) captured using DSO for Clock (CP), Data input-1 (1D) and Output (1Q), When the VCC is ON.

As mentioned earlier, I’m getting output pin-5 (1Q) as HIGH, when the CP is in low state. We have two CCA and the mentioned issue is observed in both.

[TomasVaverka]

Hello Jeevaaraam,

Thanks for your inquiry. This question is related to the Standard Products business. We would like to inform you that NXP has divested it´s Standard Products business on Feb 6th 2017. This new standalone company is called “Nexperia”, headquartered in the Netherlands, and is a world-class leader in Discretes, Logic and MOSFETs.

We would like to ask you to re-enter your inquiry at the Nexperia support web page: www.nexperia.com/support. Thank you!

Best regards,

Tomas