This article presents the NXP hardware platforms and the MathWorks and NXP software tools used to build an automotive radar application. The development workflow is anchored in the MathWorks example "Radar Signal Simulation and Processing for Automated Driving," which provides a reference architecture spanning driving-scenario simulation, radar modeling, and signal processing. The resulting signal-processing chain is then adapted and deployed onto NXP radar hardware using NXP-specific toolboxes and hardware accelerators.
This article is part of the Radar Application Development Series, which describes the complete workflow for developing, deploying, and optimizing automotive radar applications on NXP radar platforms. The purpose of this article is to introduce the overall software and hardware environment and show how the different tools, hardware components, and processing engines fit together within a radar development workflow.
The next article in this series, "Radar - Processing Chain," will explore in depth each processing block presented in the Radar Signal Processing section: Range FFT, Doppler FFT, Non-Coherent Combining, CFAR Detection, Clustering, and Direction-of-Arrival (DoA) estimation.
The starting point for the radar application is the MathWorks reference example, which models a complete automotive radar system end to end.
The workflow begins by defining a highway driving scenario using the Automated Driving Toolbox (drivingScenario), where vehicles and traffic participants are modeled. The ground-truth generated data then feeds the radar model.
Figure 1: MathWorks example bird's-eye plot with Radar detections
A 77 GHz FMCW radar is parameterized from high-level system requirements such as:
The example then builds a transceiver model with antenna arrays, transmitter/receiver components, and signal-propagation effects, generating synthetic detections that estimate the position and velocity of surrounding vehicles.
For the NXP application, the reference architecture is divided into two domains:
Executes entirely within MATLAB, and is responsible for:
Contains the processing chain deployed on the S32R45 platform:
The Radar Signal Processing domain forms the basis of the embedded radar application deployed on the S32R45 Evaluation Board.
The primary processing platform is the NXP S32R45 Evaluation Board, a development platform for high-performance 77 GHz radar applications such as adaptive cruise control, autonomous emergency braking, and cascaded imaging radar. It integrates several specialized processing engines optimized for radar workloads.
| Processing engine | Role |
|---|---|
| 4x Arm® Cortex®-A53 cores | Application-level processing, radar control, clustering, and object management |
| SPT Accelerator | Optimized FFTs and high-throughput radar signal-processing kernels |
| BBE32 DSP | Vectorized signal processing, detection algorithms, and custom radar kernels |
| LAX Accelerator | Matrix and linear-algebra operations for accelerated angle estimation |
Figure 2: S32R45 block diagram
The TEF82xx is a fully integrated 76-81 GHz RFCMOS automotive radar transceiver providing the RF front end for signal generation and capture. It integrates 3 transmit channels, 4 receive channels, ADCs, a low-phase-noise VCO, and a phase rotator, and is fully compatible with the S32R45.
In the current application, the input signal is sourced from simulation rather than hardware, so the TEF82xx is not actively used. It is included as a placeholder for future hardware-in-the-loop and real-sensor integration.
The radar application combines MathWorks toolboxes for algorithm development with NXP toolboxes and tools for deployment and accelerator integration.
| Tool | Role in the workflow |
|---|---|
| Radar Toolbox | FMCW waveform generation, propagation modeling, detection, and analysis |
| Automated Driving Toolbox | Scenario modeling, road/vehicle simulation, and ground-truth generation |
| Tool | Version | Role in the workflow |
|---|---|---|
| S32 Design Studio for S32 Platform | 3.5 | IDE, compiler, debugger, and deployment environment for the S32R45, including its accelerators |
| NXP Model-Based Design Toolbox for SPT | 1.9.0 | Bit-exact SPT simulator integration and rapid prototyping in MATLAB |
| NXP Model-Based Design Toolbox for RADAR | 1.0.0 | MATLAB integration for S32R45; SPT/LAX kernel execution, code generation, and PIL workflows |
| NXP Radar SDK (S32R45) | 1.2.0 | Optimized radar algorithms, accelerator libraries, SPT/LAX kernels, and embedded deployment infrastructure |
Together, these tools act as the gateway between the MathWorks and NXP ecosystems, enabling algorithm development, simulation, code generation, deployment, and SIL/PIL validation within a common workflow.
Once the FMCW echoes are generated or captured, the signal-processing chain transforms the radar cube into a list of detected objects. The application currently implements the following stages.
| # | Stage | What it does | Runs on |
|---|---|---|---|
| 1 | ADC Acquisition | Digitizes the beat signal into a radar data cube, using samples x chirps x antennas | TEF82xx ADCs → S32R45 |
| 2 | Range FFT | Fast-time FFT converts beat frequency into target range | SPT accelerator |
| 3 | Doppler FFT | Slow-time FFT resolves velocity, producing the processed radar cube | SPT accelerator |
| 4 | Non-Coherent Combining | Combines the magnitude of the range/Doppler-processed radar cube across channels, producing the range-Doppler magnitude matrix | SPT accelerator |
| 5 | CFAR Detection | Applies Constant False Alarm Rate thresholding on the range-Doppler magnitude matrix to detect possible targets | BBE32 DSP |
| 6 | Clustering | Groups neighboring detections, for example using DBSCAN, into physical objects | Cortex-A53 cores |
| 7 | Angle / DoA Estimation | Estimates azimuth/elevation across the antenna array, using methods such as beamforming or MUSIC | LAX accelerator |
The output of the chain is a list of detected objects with range, relative velocity, and angle of arrival.
The current application focuses on signal processing and object detection. Planned enhancements include:
The MathWorks reference example executes entirely within MATLAB. During deployment, the example is partitioned into the Environment Simulation block and the Radar Signal Processing block, where the computationally intensive signal-processing functions are replaced with NXP-optimized implementations from the Radar SDK.
This delivers faster execution, reduced CPU utilization, and accelerator offloading on the S32R45.
The development tools must be installed in the following order to ensure that all external dependencies required by the NXP MBDT for RADAR are available before it is configured:
After NXP MBDT for RADAR is installed, the integration of S32 Design Studio and S32R45 Radar SDK is performed using the MATLAB Live Script:
mbd_lax_dependencies_path.mlx
The script is located at the root of the NXP MBDT for RADAR installation. Running this script configures the required dependency paths and establishes the connection between MATLAB, the NXP Model-Based Design Toolbox for RADAR, S32 Design Studio, and the S32R45 Radar SDK.
Once the script is completed successfully, the environment is ready for simulation, code generation, accelerator kernel execution, and Processor-in-the-Loop (PIL) validation.
The NXP toolboxes ship as MATLAB Toolbox packages (.mltbx) and can be installed in three ways:
This article introduced the software environment, hardware environment, deployment workflow, and high-level radar signal-processing architecture.
The next article, "Radar - Processing Chain - RSDK," will provide a detailed analysis of each processing block presented in Section 5:
It will also explain how these algorithms are mapped onto the S32R45 processing resources and how the NXP Radar SDK accelerates the execution of each stage.