Verification models for free I3C slave IP

[stephan_dolezal]

I'm using the free NXP I3C slave IP (https://github.com/NXP/i3c-slave-design) and found it very helpful to write a minimalistic I3C master simulation model for testing the reaction of the I3C slave to understand how it works in detail.

Is there an official I3C master simulation model for verifying my design? Or are there any hardware devices capable of serving as an I3C master for verification?

Thanks and best regards,

Stephan

[Fabian_R]

Hello Stephan,

Currently, we do not have an IC3 master simulator nor hardware available, Although it is scheduled for the following months to launch new I3C capable silicon.

Have a great day,
Fabian

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[chengxiaolei]

HI Fabian

can you provide the tst_i3c_master_model.v file ? it is not in packet zip;