Could you please confirm whether the PCIe reference clock is required if the PCIe subsystem on the P1022NXN2HFB device isn’t being used?
If a Serdes is not used, its reference clock is not needed. Note that settings of cfg_serdes_ports [0:4] allow to disable Serdes1 or Serdes2 or both.
Please refer to "18 SerDes Interface Pin Recommendations" in the attached document.
