access NT3H2211 via libMPSEE

[geraldherbel]

What is the content of the buffer used for the I2C_DeviceWrite() or I2C_DeviceRead() API's when attempting to access the SRAM for NT3H2111 device?  The Data Sheet indicates a Read Command Code of 0x30  but in the Sample libMPSSE code that I discovered, the Command Code was not present  (only a single byte of value 0 which was used to read the Serial Number).  Does this imply that the APIs add the command code for the NT3H2111 (which doesn't seem right because that would mean that libMPSSE is specific to the NT3H2111 device)???

[Kan_Li]

Hi Gerald,

Are you referring to the example as below?

i2cNumBytesToTx = 0;  i2cData[i2cNumBytesToTx++] = 0x00;   // MEMA page   i2cStatus = I2C_DeviceWrite(i2cHandle, i2cAddr, i2cNumBytesToTx, i2cData, &i2cNumBytesTxd, 0x01);  i2cStatus = I2C_DeviceRead(i2cHandle, i2cAddr, i2cNumBytesToRx, &i2cData[0], &i2cNumBytesRxd, 0x03);

Actually it is a I2C reading process of 
.

Please refer to the following for details.

Have a great day,
Kan

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[geraldherbel]

Kan‌

My question is what information to copy into the buffer used by those two APIs??

 My example places a single byte ( value of 0) into the buffer.  But the NT3H2111 data sheet  describes a Read Command code of 0x30 followed by an address (that is two bytes minimum).  Those two are not the same!!

What is the the precise info for the API buffer used in libMPSSE .?

[Kan_Li]

Hi Gerald,

Yes, those two are not the same, but I think maybe you have some misunderstanding with the command code 0x30, you know , NTAG I2C has two interfaces: I2C and RF interface, and 0x30 is one of the NFC commands issued from RF side, so if you want to access NTAG from I2C side, no need to use the NFC commands.

Hope that makes sense,

Have a great day,
Kan

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[geraldherbel]

Thanks Kan  for that speedy reply!!  Yes you are correct, I  misread the PDF document and didn't notice that I was looking at the NFC interface description.   Sorry about that.
  So it looks like I provide only the Memory Block Address in  those two APIs.  So for access to SRAM, I provide a block address in the range  of 248 to 251 ???

[Kan_Li · Accepted solution]

Hi Gerald,

From the I2C perspective, it is.

Have a great day,
Kan

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