PN7462-Cannot debug after Release version code flash

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PN7462-Cannot debug after Release version code flash

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sanath_rai
Contributor III

Hello,

I have been  working on PN7462 NFC controller.i am building my application on Door access code.

Till now i was working in Debug mode in MCUXpresso IDE where initially i used to dump the user_ee.bin file to my PN7462 via MCUxpresso GUI and then i used to debug the code using MCU xpresso IDE and everything was working fine.

ISSUE1:

I changed debug mode to release mode and flashed the code using MCUXpresso IDE and after that when i tried to debug the code i am unable to debug using IDE.its showing below error.

Reconnected to existing link server
Connecting to probe 1 core 0 (using server started externally) gave 'Ee(42). Could not connect to core.'
Connecting to probe 1 core 0 (using server started externally) gave 'Ee(42). Could not connect to core.'
Connecting to probe 1 core 0 (using server started externally) gave 'Ee(42). Could not connect to core.'
Server OK but no connection to probe 1 core 0 (after 3 attempts) - Ee(42). Could not connect to core.
Failed on connect: Ee(42). Could not connect to core.
No connection to chip's debug port
(100) Target Connection Failed
Unable to perform operation!
Command failed with exit code 1

then we replaced the IC in the board and dumped the user_ee.bin file to my PN7462 via MCUxpresso GUI .

Now the same issue is replicating even here.

I dont understand whats the issue?

ISSUE2:

As i mentioned i have built my code on Door Access user code.

I tried putting the code in Standby mode by enabling the PHFL_ENABLE_STANDBY macro.

after that my High speed UART(HSU) is not responding how can i wake up that any particular setting needed?

Thanks and Regards

Sanath Rai.

 

6 Replies

392 Views
estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

Is the board you are referring to the development kit or is it your custom board?

If it is the development kit ,  have you tried using the the guidance of the UM10883?

Regards,
Estephania

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sanath_rai
Contributor III

Hello,

Sorry for the delayed response.

Right now we are using our custom board.

The first issue is solved .i created a new workspace and dumped my code in Debug mode  and i was able to debug.

But the second issue  which i have mentioned still exists.

I will explain my application briefly:

I have developed my application on Door access application where  we tap the NFC tag it throws out UID via SPIM.

Originally the Door access code is designed where the UID and data is been thrown out via HSU(High speed UART)

but i have changed it to SPIM interface.

And the HSU i am using to interface with another device in our application. Everything is working fine in normal mode,

but when i tried putting the code in Standby mode by enabling the PHFL_ENABLE_STANDBY macro.

The HSU is not responding . Is there any way to wake it up? or what might be the issue?

Regards

Sanath Rai

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

Could you please help me check the following UM ? If you check the UM10858 there are more details of the power modes on chapter 8.3 Power modes 

In the chapter 8.3.2.1 you can see that the device will restart from the beginning when coming out of the standby mode.

pastedImage_1.png

Hope this helps.

Regards ,
Estephania

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sanath_rai
Contributor III

Hello  Estephania,

I have gone through the hardware user document  (UM10858) and the software user manual(UM10913) .we feel that hard power down mode is the best mode for the lowest power consumption.but i have a doubt here.we found its by using the RST_N pin.Any example will be helpful .

How can we put the on PN7462 into hard power mode  using the software or just by making the RST_N pin low by giving it to some GPIO.

In document UM10858 section 8.3.5 it's given as below

8.3.5 Hard Power Down Mode
This is the lowest power mode allowing for the highest reduction of the power
consumption. All clocks are turned off, all LDOs are turned off, except the MLDO which is
set to the low power mode
The PN7462 family enters the Hard Power Down mode when RST_N is set to zero or the
VBUS voltage is going below 2.3 V.
The PN7462 family exits the Hard Power Down mode, when RST_N pin is set to high
level and VBUS voltage goes above 2.3 V

But in section 3.3.1.4 in UM10913 (software user manual) it is given as below

RST_N pin behavior
The SecRow contains the bits that control the behavior of HW related to the RST_N pin when pad voltage is not available. Two parameters define the RST_N pin behavior, 

RST_N pull-down and RST_N value.
The phhalSysSer_OTP_SecrowConfig() is used to control the RST_N pin behavior.


Table 6. RST_N pin parameters
RST_N pull down RST_N value HW operation
0 X[1] pad voltage availability is always assumed in this system;
IC checks the status of RST_N pin at POR and enters
either HPD or starts ROM booting
1 1 pad voltage availability is not assumed in this system; IC
does not check the status of RST_N Signal and starts
ROM boot normally upon POR

Regards

Sanath 

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello,

Please help me check this post

https://community.nxp.com/thread/453296 

Regards,

Estephania

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sanath_rai
Contributor III

Hi Estephania,

Sorry for the delayed response as i was into some other work.I will get back to you as soon as check the document given by you

Sanath