Bit field Hi, I am using MC9S12DG256 controller and IDE is CodeWarrior 5.2. When I am disabling the option bit field size reduction , the memory allocation starts from mid instead of start. for example my variable is of type int it starts from 8 instead of 0. I want to start from 0. Please find the screen shot attached. Re: Bit field Hi, the game you are playing is related to the defined sizes of bitfield elements (unsigned char, unsigned int) and then MSB. LSB order, MSb, LSb order. I suggest you to test combinations simply with different options after reading the help .... If you want more info about bitfields I suggest to go through all appearnces in Plus when you select an item it can show more options with the same name. Open each of them because each of them direct to different contet. ... or go to your instalation dir c:\Program Files (x86)\Freescale\CWS12v5.2\Help\pdf\ open file Compiler_HC12.pdf and search for each existence of bitfield keyword. Best regards, Ladislav

Ram size in Linker File for S32K3 RTD Hello team, Apparently when creating a new RTD project and checking the linker file, there is a reserved section of SRAM that is marked as "used by the HSE" in a comment and apparently the linker never configures the last 48kB of SRAM1 available, however the HSE is not using any SRAM from the SRAM1 so this would need to be changed to match the whole SRAM available for the application instead of ending at 0x20443FFF, it should be covering all the way up to 0x2044FFFF. I think this applies for the S32K3X4 variants that have SRAM1 available. This needs to be fixed in the RTD releases. Best Regards, Jesus Cinco Priority: MEDIUM RTD Source: NXP Internal Re: Ram size in Linker File for S32K3 RTD Hi @Jesus_Cinco, In the past, there is a similar case (BENV-150) that was raised by another customer. The RTD team has observed an issue when accessing the last 48 KB of SRAM on the S32K344 derivative with certain HSE firmware versions. So, to avoid any potential issues with HSE FW, RTD package continues to reserve this last 48 KB of SRAM for HSE usage. They contacted HSE_FW team to ask details about this issue, but until now, they have not received any responses yet. Could you help me contact HSE_FW team to confirm about this issue? The RTD team needs a confirmation from HSE_FW team to implement correct linker file. Best regards, Dan Re: Ram size in Linker File for S32K3 RTD Hello Dan, Sure I can align with the HSE Team to have this verified. Can you indicate me the FW versions tested in which the RTD team found this memory access issues? Best Regards, Jesus Cinco Re: Ram size in Linker File for S32K3 RTD Hello Dan, Understood, I will verify this with the HSE Team. Best Regards, Jesus Cinco Re: Ram size in Linker File for S32K3 RTD Hi @Jesus_Cinco, At the present, I don't have specific information about HSE_FW version. So, I just only want to know whether there is any HSE_FW versions uses last 48KB of SRAM1 or not. Best regards, Dan Re: Ram size in Linker File for S32K3 RTD Hello Dan, I have received confirmation that there doesn't seem to be any usage of the HSE FW in that ram address range. https://community.nxp.com/t5/HSE-FW-Support/S32K3-HSE-SRAM-usage/m-p/2371421#M4410 Would it be possible to make the required changes in the RTD to include that range in the linker file? Best Regards, Jesus Cinco Re: Ram size in Linker File for S32K3 RTD Hi @Jesus_Cinco, I have seen their response. But I have a concern about this response: How to know any libraries linked within HSE FW consumes SRAM1 and block access to SRAM1? Best regards, Dan

[S32k5]Missing performance of SAF Hi teams Customer PATAC want to evaluate the boot time, They will integrate SAF into project, but The version of SAF is EAR version and no execute time of every module, especially time of scheck items. So do we have draft performance data of SAF?  Best Regards Junjie Safety_SW Re: [S32k5]Missing performance of SAF Hi @Junjie , this is usually part of quality pack - profiling report, where sCheck UM takes values from, but it is not planned to deliver for EAR releases. Would it help for some rough idea about the execution times to explore S32K3 sCheck manual? But without any guarantee how much these times will differ for real K5 device. Kind Regards, Radoslav 

I want to use multiple can rx and send with different message Id I want to use multiple Can Rx messages and I need to send same messages through different id’s. If anyone has working model please share here Re: I want to use multiple can rx and send with different message Id Hello @Sachinkumarar15, There is an existing example inside the RTD package for a simple FlexCAN configuration, along with some additional ones in our community: [RTD600 MCAL & IP] S32K3X4EVB-T172 FlexCAN Example Interrupt/Polling Example S32K344 FlexCAN_Ip TX/RX/EnhanceRXFIFO DMA test S32DS3.5 RTD400 You can modify them to receive and transmit multiple IDs. For Rx, simply modify the Rx filter, and for Tx, you can re-use the same Tx data and change the msg_id.  Best regards, Julián

K5のLPE_ADC構成に関する質問 こんにちは、チームの皆様。 K5のLPE_ADC設定についてお伺いしてもよろしいでしょうか？ LPE_ADC_CH8_P8(GPIO204)を使用しようとしたところ、以下のエラーが表示されました。 S32DSを使用すると、LPE_CMP1_IN7用にさらに1つのピン構成が作成されます。ポート設定にエラーが表示されています。 LPE_ADC_CH8_P8の設定方法を教えていただけますか？ それとも、ポート（ピン）の設定は不要で、ADCモジュールの設定のみが必要なのでしょうか？ もしそうなら、どのピンがそのような動作をしていますか？ ありがとう。 RTD 出典：直接お客様 出典：NXP社内資料 Re: Question about LPE_ADC configuration of K5 こんにちは、 @Luke_Chun さん。 はい、ADCチャネルでこのピンを設定するだけで済みます。ポート経由で設定する必要はありません。 よろしくお願いいたします。 ニ

[S32K314][RTD-SDK] CANでDMAを使用する例はありますか？ [S32K314][RTD-SDK] CANでDMAを使用する例はありますか？ Re: [S32K314][RTD-SDK] Is there a example for using DMA with CAN? なぜsexampleではDMAを選択できるのに、私のプロジェクトではできないのですか？ Re: [S32K314][RTD-SDK] Is there a example for using DMA with CAN? こんにちは、 コミュニティに投稿されたThread/例を参照してください。 https://community.nxp.com/t5/S32K/S32K3xx-FlexCAN-legacy-and-Enhanced-RXFIFO-DMA/mp/2023755 https://community.nxp.com/t5/S32K/S32K3-FLEXCAN-LEGACY-RX-FIFO/td-p/1878769 https://community.nxp.com/t5/S32K/S32K358-Legacy-RX-Fifo-with-DMA-vs-enhanced-RX-Fifo-DMA/mp/2266494 BR、ペトル

S32K394 ITCM 耐久性和启动时初始化（ECC 上下文） Hello 🙂 参考以下话题：上一张带有主题的票证：S32K394 FCCU 不可恢复的故障 NCF_S2 (ECC)- 如何识别哪个内存块触发了它？。 我有一个关于 ITCM S32K394 的问题。 的最大擦除和写入耐久性（P/E 或写入周期） ？ 像通常对 SRAM 一样 在启动 时 初始化/清除 ITCM 是否可以接受？ 我目前假设 ITCM 是 Flash，但我不确定这是否正确。能否请您确认 ITCM在 S32K394 上的物理存储器类型是 （SRAM 与闪存还是其他），以及重复初始化是否会影响耐用性？ 如有任何指向相关参考手册部分或数据表规格的指示，将不胜感激。 先行致谢。 仅供参考，@danielmartynek Re: S32K394 ITCM endurance and boot-time initialization (ECC context) 嗨，@SBalaji、 1. 它是 SRAM，因此没有闪存的限制。 2。 是的，必须在读取之前对其进行初始化，就像任何其他带有 ECC 的易失性存储器一样。 3. 它是一个 SRAM。关键区别在于，TCM（紧密耦合存储器）通过专用总线直接连接到内核。相比之下，SRAM 是通过与其他系统主控共享的交叉条开关进行访问的。 请参阅参考手册中的图 5：方框图。 此致， 丹尼尔

支持 i.MX257 与非 的 ATK 源代码 大家好， 我目前正在使用i.MX257平台，需要获取高级工具包（ATK）v1.71源代码、预编译的二进制文件和相关文档。 具体而言，我们需要包含或可适用于以下 与非 闪存型号的 ATK 闪存库： 美光：MT29F1G08ABADAWP 三星：K9F1G08U0DU00 华邦：W29N01GVSIAA 我们的目标是更新 mx25_与非.bin RAM 内核中支持的 与非 类型。如果标准版本不支持这些特定型号，我们正在寻找源代码软件包，以便按照恩智浦应用笔记 AN3985 中的说明自行调整闪存库。 社区或@nxp技术支持人员能否提供有效的下载链接或指导如何获取这些文件？ 感谢您的帮助！ Re: ATK source code for i.MX257 NAND support 你好 请提交支持单以获取 Advanced Toolkit (ATK) v1.71 源代码。 你可以找我。 顺祝商祺！ Re: ATK source code for i.MX257 NAND support 谢谢@JorgeCas

S32 design studio 3.6.4 Hello,  I am using s32 design studio 3.6.4 and RTD version 3.0.  I want to create a time delay signal using simple sine wave, a gain and output in simulink and generate c code. Then from my dio example in s32 design studio i want to call that function.  This is the error i am getting. Can anyone please see what could be the issue. 

The RTD version used in FSS FW and FSS AUX sample compatibility Hello Team, Software package: SDK_1_0_5_3 Customer: Schaffler The RTD versions used in the released FSS FW and FSS AUX are not compatible with the expected GrayVIP version, which may cause confusion for customers. GrayVIP expects version TS_T31D62M28I0R0, while the release currently uses TS_T31D62M18I0R0. As a result, after importing the project and saving it again, significant configuration changes can be observed in IPCF, NETC, and EcuC XDM, beyond the intended version updates. In particular, when customers switch GrayVIP from an older version to this release, code generation may not behave as expected.   Is there a workaround available to resolve this incompatibility in the current release, or can we confirm that the observed changes do not impact code generation or system functionality? Customers expect that this incompatibility can be avoided in future releases, as it currently leads to unnecessary debugging effort and time loss.   Best regards, Tangsheng.     FSS_FW GRAY_VIP Priority: MEDIUM Re: The RTD version used in FSS FW and FSS AUX sample compatibility Hello @Tangsheng_Zhou,  The development teams have picked up the case and will provide an answer as soon as possible. Best regards,  Radu Re: The RTD version used in FSS FW and FSS AUX sample compatibility Hello @RaduBraga  1. Can we please get a status update here? 2. What is the associated JIRA ticket? 3. Can you confirm a configuration fix will be made for GrayVIP 1.0.6.0 ? Thanks. Re: The RTD version used in FSS FW and FSS AUX sample compatibility After a discussion with the GrayVIP development team a jira ticket was created for the FSS team.  Re: The RTD version used in FSS FW and FSS AUX sample compatibility Hi Radu, Could you please provide the JIRA ticket link for the FSS ticket you mentioned? Thanks. Re: The RTD version used in FSS FW and FSS AUX sample compatibility Hello @RaduBraga  Could you please provide the JIRA ticket link for the FSS ticket? Thanks! Tangsheng. Best regards.

Problems with NTAG DNA 424 - WriteData - Length Error Hello, I am trying to use the NTAG 424 chip for my anti-tamper application. For this I implemented the AES authentication and cryptographie for sending and receiving commands. However when I am trying to issue the writeData command with some dummy data, I get the error: 917E: "Length Error"". The data I am trying to send is the following cmd_header = 02000000040000 cmd_data = 00D1FF00 (before padding) cmd_data = 00D1FF00800000000000000000000000 (after padding) now the complete command which I send looks like this: cla cmd P1&2| Lc |ISO Header          | encrypted Data | 90 8D 00 00    1F 02 000000 040000 6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3 00 I dont think that I made errors in the encryption, because I implemented a unit test which replicates the results of the example in the AN12196 application note (Table 17). Also, the PICC returns an Length error, which according to the Documentation means "Command size not allow". I do not understand this error, but I dont think it has something to do with my encryption. So does anyone know what I am doing wrong?  Best regards, Phil Update: So I can definitely say that the fault has nothing to do with my encryption, because I can correctly parse the response from the chips for commands like the GetTTStatus and the GetCardUID. Additionally I can correctly encrypt and send the SetConfiguration command, which tells me that I definitly send the correct command. Contact Smart Card Reader ICs Re: Problems with NTAG DNA 424 - WriteData - Length Error Dear @Jonathan_Iglesias ,  I am checking this post because I am having the same issue here. I followed the exact same steps in your post, but I keep getting 917E response. Do you think it might be due to my card reader? I am using an ACS ACR1251U. Also, you said: "check that you have changed the file settings so it supports encrypted communication and which keys are allowed to perform this actions." How do I check that? Regards, Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi, I know this message was from a while ago, but I'm curious to know how you run the APDU commands on your NTAG424. I'm having issues with running commands. thanks. Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi Philippe Petit,  Please let me know if my answer above was helpful. Looking forward to your answer. Have a great day ! BR Jonathan  Re: Problems with NTAG DNA 424 - WriteData - Length Error Hi  Please check the following : -----------ISO 14443-3 ACTIVATION------------------ phpalI14443p3a_ActivateCard--------ENTRY-------- Send to card: 26 Recv from card: 4403 Send to card: 9320 Recv from card: 88046F0FEC Send to card: 937088046F0FEC Recv from card: 04 Send to card: 9520 Recv from card: 2AAA618061 Send to card: 95702AAA618061 Recv from card: 20 phpalI14443p3a_ActivateCard--------LEAVE-------- pUidOut=046F0F2AAA6180 pSak=20 pMoreCardsAvailable=00 [STATUS = SUCCESS] --------------------ISO 14443-4--------------------------------- phpalI14443p4a_ActivateCard--------ENTRY-------- bFsdi=08 bCid=00 bDri=03 bDsi=03 Send to card: E080 Recv from card: 067777710280 Send to card: D0110F Recv from card: D0 phpalI14443p4a_ActivateCard--------LEAVE-------- pAts=067777710280 [STATUS = SUCCESS] -----------------ISO FILE SELECT------------------------------- phalMfNtag42XDna_IsoSelectFile--------ENTRY-------- bOption=0C bSelector=04 pFid=10E1 pFid=10E1 bDFnameLen=07 pDFname=D2760000850101 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=00A4040C07 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=D2760000850101 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 00A4040C07D276000085010100 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=9000 [STATUS = SUCCESS] Recv from card: 9000 phalMfNtag42XDna_IsoSelectFile--------LEAVE-------- [STATUS = SUCCESS] -------------------AUTHENTICATION TO KEY 00-------------------------- phalMfNtag42XDna_AuthenticatEv2--------ENTRY-------- bAuthOption=01 wOption=FFFF wKeyNo=0000 wKeyVer=0000 bKeyNoCard=00 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=9071000002 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=0000 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 9071000002000000 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=E21768618E1FDB9D93F596551CE06E6B91AF [STATUS = SUCCESS] Recv from card: E21768618E1FDB9D93F596551CE06E6B91AF PICC-to->PCD E(Kx, RNDB): E21768618E1FDB9D93F596551CE06E6B Plain RNDB = CE86E6E968F45458B6762D28D91764B8 Plain RNDA = D5D29FF822CD1A158E59A42AA74AA245 Encrypted (RndA || RndB') = 7B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=90AF000020 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=7B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 90AF0000207B57022C027C5124E19AC54D5E38A10A732F64C98AA63F80F9536F4D889C257F00 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E59100 [STATUS = SUCCESS] Recv from card: 1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E59100 PICC-to->PCD E(Kx, TI||RndA'||PDcap2||PCDcap2): 1820F5BC0D050F4CAA73E388C86BE03188B85535D1B7682A9818ACEDA8D2A9E5 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = A55A00010080D5D2517EC42472E15458B6762D28D91764B88E59A42AA74AA245 MAC = 9E2BC594A132DD9FA2C236A7900BC709 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 5AA500010080D5D2517EC42472E15458B6762D28D91764B88E59A42AA74AA245 MAC = 13930ABCFB85B996262109D34C08726E Encrypted SessionKeyEnc KSesAuthENC = 9E2BC594A132DD9FA2C236A7900BC709 Session KeyType ENC = 0000 Encrypted SessionKeyMAC KSesAuthMAC = 13930ABCFB85B996262109D34C08726E Session KeyType MAC = 0000 Transaction Identifier = 9092A1C6 phalMfNtag42XDna_AuthenticatEv2--------LEAVE-------- bPcdCapsOut=000000000000 bPdCapsOut=000000000000 [STATUS = SUCCESS] AUTHENTICATED ----------------------WRITE DATA TO FILE---------------------------- phalMfNtag42XDna_WriteData--------ENTRY-------- bOption=30 bIns=01 bFileNo=02 pOffset=000000 pTxData=6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3 pTxDataLen=180000 Encrypted (RndA || RndB') = 007D004AD1DF8F85B07D9CF17000DE2A Encrypted (RndA || RndB') = 75B2F5DDC646CA4C70B9A64F9D7888C2 Encrypted (RndA || RndB') = 3BA4362223091B1BFFE940229FA36A67 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 8D00009092A1C60200000018000075B2 MAC = 5B85393206D2041DEEF7AA344C0FAB66 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = F5DDC646CA4C70B9A64F9D7888C23BA4362223091B1BFFE940229FA36A67 MAC = 43153DFF079B421A4A8E31AA92407AE5 phpalI14443p4_Exchange--------ENTRY-------- wOption=8000 pTxBuffer=908D00002F phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=02000000180000 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=75B2F5DDC646CA4C70B9A64F9D7888C2 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] phpalI14443p4_Exchange--------ENTRY-------- wOption=C000 pTxBuffer=3BA4362223091B1BFFE940229FA36A6715FF9B1A8EAA40E5 phpalI14443p4_Exchange--------LEAVE-------- [STATUS = SUCCESS] Send to card: 908D00002F0200000018000075B2F5DDC646CA4C70B9A64F9D7888C23BA4362223091B1BFFE940229FA36A6715FF9B1A8EAA40E500 phpalI14443p4_Exchange--------ENTRY-------- wOption=4000 pTxBuffer=00 phpalI14443p4_Exchange--------LEAVE-------- ppRxBuffer=87E6C1369D4C9F019100 [STATUS = SUCCESS] Recv from card: 87E6C1369D4C9F019100 MAC Input Data = Cmd||CmdCtr||TI||CmdHeader||E(CmdData) MAC Input Data = 0001009092A1C6 MAC = 568770E6F1C1E5362D9D844CCF9FA301 phalMfNtag42XDna_WriteData--------LEAVE-------- [STATUS = SUCCESS] Please check this process, this is the entire process I used, please check that you have changed the file settings so it supports encrypted communication and which keys are allowed to perform this actions. and check the LC of the APDU command. if you have more questions please let me know. Have a great day ! BR Jonathan Re: Problems with NTAG DNA 424 - WriteData - Length Error Hello Jonathan, thank you for your answer. you are right if we are in plain mode. If we are in plain mode, and I want to write the bytes (6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3), then I have to have a length of 24 in my header.  If, however, I want to write the 4 bytes as specified in my question (in encrypted communication mode), then it does not work to put a length of 24 (18h) in the header. So my workaround for the moment is to write the 4 bytes in plain communciation mode (in which I dont have to perform the encryption) and then to lock the file with the desired key. However I would like to know how to write in encrypted mode? The Data-sheet is a bit unspecific in this term, and the application note is just plainly wrong (the application note has also a couple of other errors see for example) Thanks for  Re: Problems with NTAG DNA 424 - WriteData - Length Error Hope you are doing great,  I believe the problem is thar the lenght inside the CMD header is incorrectly please  check datasheet Figure 27  the number of bytes to be written  should be 24 bytes  (6688A4D75482FC972C2447A1A20F0AC9C073C1CF506B2BD3) BR Jonathan 

[CHARGEX][SE050E]Ed448 (EdDSA) vs X448 (ECDH) support on SE050E2HQ1/Z01Z3Z for ISO 15118-20 Hi Experts, The customer is CHARGEX from Germany,  and they are currently developing an EVSE communication controller targeting the ISO 15118-20 (V2G) standard. Their host MCU communicates via I2C with the EdgeLock SE050E (Specific OPN: SE050E2HQ1/Z01Z3Z, running IoT Applet 7.2). They are attempting to implement "Cipher Suite 2" requirements, which necessitate 448-bit Edwards curves. However, they have encountered a discrepancy between the SE050E marketing documentation and the provided Plug & Trust middleware (Simw-top) headers, and we need clarification on the hardware's exact capabilities. Application Note AN13014 states that the SE050E and SE051 add "support for Edwards Curve448." However, looking at the middleware header se05x_enums.h, only definitions for the Montgomery form for key exchange (kSE05x_ECCurve_ECC_MONT_DH_448 = 0x43) and no definitions for Ed448 EdDSA signing. Is this a doc issue here? I also find https://www.nxp.com.cn/docs/en/application-note/AN13645.pdf which states "EdgeLock SE05x supports ECC keys with future proof curves and high key length: Brainpool (160 to 512 bits), NIST (192 to 521 bits), Edwards (curve 25519 and curve 448), Montgomery (curve 25519 and curve 448) and Koblitz (160 to 256 bits).", but both the APDU spec and SE05x configuration (https://www.nxp.com.cn/docs/en/application-note/AN12973.pdf  https://www.nxp.com.cn/docs/en/application-note/AN12436.pdf ) just have Montgomery (curve 25519 and curve 448) supported. Please kindly clarify. Best Regards, Kan Re: [CHARGEX][SE050E]Ed448 (EdDSA) vs X448 (ECDH) support on SE050E2HQ1/Z01Z3Z for ISO 15118-20 Hi @nxg11900 ， Thanks for the clarification! I will share this info with the customer. Have a great day! Best Regards, Kan Re: [CHARGEX][SE050E]Ed448 (EdDSA) vs X448 (ECDH) support on SE050E2HQ1/Z01Z3Z for ISO 15118-20 Hi Kan, we don't support  Edwards Curve448. this is documentation error in 2 docs and we will update the docs. and in An13014 it is support for Montgomery curve 448 which is added and not edwards curve 448. We willl correct this in doc kind regards, Parth

MIMXRT1170-EVK フラッシュICの問題 お客様、 当社はMIMXRT1170-EVKをベースにカスタム基板を設計しました。 NOR Flash 128Mb QPI/QSPI、IS25WP128-JBLE、パッケージ：SOIC-WIDE-8 を使用したカスタムボードが動作しません。IC は、販売代理店の Mouser、DigiKey から購入しました。 Avnet社はOEM ISSIからIC IS25WP128F-JBLEを入手し、最初にMIMXRT1170-EVKに組み込みましたが、動作しませんでした。 評価ボードからICを交換すると、正常に動作します。 解決策、またはICのピン交換をできるだけ早く提供していただくようお願いします。 よろしくお願いいたします。 ラヴィ・カント・ヴァルマ HAL、ハイデラバード、インド Re: MIMXRT1170-EVK Flash IC Issue こんにちは、 @Ravi07011983 さん。 あなたの調子が良いといいのですが！ 先ほど話し合ったように、SFDCでは常に同期を保ちましょう。良い一日をお過ごしください！ よろしくお願いします、 ギャビン Re: MIMXRT1170-EVK Flash IC Issue お客様、 評価ボード MIMXRT1170-EVK NOR Flash 128Mb QPI/QSPI、IS25WP128-JBLE、パッケージ:SOIC-WIDE-8 が動作しません。 解決策の提供を依頼します。

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RTD 3.0.0に付属するS32K1 FTM GPTドライバ チームの皆さん、こんにちは。 FTM 1 CH0をGPT割り込みソースとして有効にしても、コードジェネレータによって割り込みが自動的に有効になるわけではありません。しかし、FTM0 CH0で同じことを行うと、割り込みが有効になります。これは、例 Ftm_Gpt_Example_s32K148 で使用されているケースです。行を手動で追加します #define FTM_1_CH_0_CH_1_ISR_USED generated/include/ ディレクトリ内の Ftm_Gpt_Ip_Cfg_Defines.h は機能します。 バグかどうか確認してください。 RTD S32_CONFIG_TOOL S32DS Re: S32K1 FTM GPT driver that comes with RTD 3.0.0 こんにちは@ Nhi_Nguyen 迅速な対応ありがとうございました。 Re: S32K1 FTM GPT driver that comes with RTD 3.0.0 こんにちは、 @Senlent さん。 あなたの問題点が理解できました。これは確かに問題だと思います。チケットが作成されました：ARTDCT1-1122。回避策として、前回の回答で述べたように、FTM1の割り込みを有効にしたい場合は、FTMインスタンスを2つ構成してください。 よろしくお願いいたします。 ニ Re: S32K1 FTM GPT driver that comes with RTD 3.0.0 こんにちは、@ Nhi_Nguyen おっしゃることは理解できます。 これが私がそれを改造した方法です。 この変更は問題を引き起こすだろう。この問題が再現できますか？ Re: S32K1 FTM GPT driver that comes with RTD 3.0.0 こんにちは、 @Senlent さん。 このチャネルの割り込みを有効にする前に、FTM1_CH_0を設定しましたか？このような： よろしくお願いいたします。 ニ

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S32K1 弱定义不能被强定义覆盖。 你好，恩智浦 我们遇到过这样一个问题，即一个弱定义的中断处理函数无法被库中的强定义所替代。当我们将 SDK 编译成静态库并将其添加到 APP 时，发现 CAN0 中断处理函数无法进行强定义。 我使用的 IDE 是 S32DS ARM 2.2，SDK 版本是 3.0.0，编译器版本为 gcc 6.3。 以下是我的 Demo 测试情况： 如果在启动时保留弱定义的中断处理函数，中断向量表的内容将是弱定义的函数。 ② 如果我注释掉启动时定义较弱的中断处理函数，就可以正确定义 CAN 中断处理函数。 造成这种现象的原因是什么？测试 Demo 的源文件和编译静态库后的文件附后。 Re: S32K1 weak cannot be overridden by strong definitions. 你好@武仙龙 这可能与编译器的某些设置有关。我有时间就会处理你的问题，这不是一个紧急问题。 Re: S32K1 weak cannot be overridden by strong definitions. 你好，@Senlent 感谢您的支持。只有在使用静态库文件 .a 时，才会出现弱定义不能被强定义替换的问题。并在静态库中使用强定义。 基于 S32K146_UJA1169_SDK300，我将 SDK 编译成静态库（.a 文件）并加载到应用程序中，例如我的 S32K146_UJA1169_Lib_SDK300。这样我就能重现问题了。除非我注释掉弱定义，否则 CAN0_ORed_0_15_MB_IRQHandler 不会被加载到中断向量表中。 敬上， xianlong Re: S32K1 weak cannot be overridden by strong definitions. 你好@武仙龙 我没有完全理解你的问题。 我测试了您提供的项目"S32K146_UJA1169_SDK300.zip," 并按照您的方法禁用"def_irq_handler CAN0_ORed_0_15_MB_IRQHandler。" 两者的编译结果完全相同，没有任何差别。 Re: S32K1 weak cannot be overridden by strong definitions. 造成这种现象的原因是什么？测试 Demo 的源文件和编译静态库后的文件附后。                  

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