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Programming i.MXRT with MCUXpresso IDE and BOOT i.MX RT is NXP new product. Recently we often have customers asking the possible methods of programming code to i.MX RT in both developing stage and manufacturing stage. In this article, I will summarize the programming methods based on MIMXRT1050-EVKB board. 1.    Using MCUXpresso IDE programming 1.1.    Using MCUXpresso IDE debugger programming 1.2.    Program flash action using LinkServer/etc. 1.3.    Program target with GUI Flash Tool 2.    DAP-Link (OpenSDA MSD drag/drop) 2.1.    Boot Settings 2.2.    Check versions of SDK and DAP-Link 2.3.    Generate Binary file 2.4.    OpenSDA MSD drag/drop steps 3.    Using  MFGTool program with Boot 3.1.    Boot Settings 3.2.    Check versions of SDK and DAP-Link 3.3.    Generate Binary file 3.4.    Using MFGTool burning HyperFlash with BOOT
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Electrification—HV EV Power Inverter System Utilizing the GD3100 Product training of GD3100 IGBT GDIC with integrated isolation for high voltage and high current electric vehicle and Industrial invertors. Product training of GD3100 IGBT GDIC with integrated isolation for high voltage and high current electric vehicle and Industrial invertors.
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AOI and Crossbar features The AOI and Crossbar modules are inregrated in DSC, Kinetics KV and i.mxrt families, user can use them to generate complicated trigger signal for the on-chip peripherals. The DOC discusses the AOI function, crossbar fuction based on KV58. It gives the example, the example demos how to implement AND operation of two signals via crossbar switch A and B and AOI modules. The two logic signals are connected to the pads of KV58, and routed to AOI inputs via Crossbar switch B, the AOI sub-module0 implements the AND operation of the two signals, and output the AND output signal Event0  to pad of KV58 via crossbar switch A. Connect input pads and output pad of KV58 to oscilloscope, from the waveform of the three signals on scope, we can see that the AND logic  is implemented. Kinetis V Series MCUs
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EDAC L1 and L2 cache error detection and correction on LS1043 ARM Cortex A57 and A53 L1/L2 cache error reporting The attached patch adds error detection for A53 and A57 cores. Hardware error injection is supported on A53. Software error injection is supported on both. For hardware error injection on A53 to work, proper access to L2ACTLR_EL1, CPUACTLR_EL1 needs to be granted by EL3 firmware. This is done by making an SMC call in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting.   CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used for checking L1 and L2 memory errors. However, only A53 supports double-bit error injection to L1 and L2 memory. This driver uses the hardware error injection when available, but also provides a way to inject errors by software. Both A53 and A57 supports interrupt when multi-bit errors happen.   To use hardware error injection and the interrupt, proper access needs to be granted in ACTLR_EL3 (and/or ACTLR_EL2) register by EL3 firmware SMC call. Correctable errors do not trigger such interrupt. This driver uses dynamic polling internal to check for errors. The more errors detected, the more frequently it polls. Combining with interrupt, this driver can detect correctable and uncorrectable errors. However, if the uncorrectable errors cause system abort exception, this driver is not able to report errors in time.     Building PPA Image Please make sure the PPA source which you are using includes commit 781d7b513c2b44e7, PPA source code in LSDK later than1809, which includes this commit, so you could use PPA image provided in LSDK 1809 or the later release. In addition, You need to enable "dbg" when building PPA. If you use LSDK build environment, please add "dbg" in ppa build command in packages/firmware/Makefile as the following, then rebuild ppa with command "$ flex-builder -c ppa -m ls1043ardb" and get ppa image in build/firmware/ppa/soc-ls1043/ppa.itb. socname=`echo $(MACHINE)|tr -cd [:digit:]` && \ ./build rdb-fit dbg ls$$socname && cp soc-ls$$socname/build/obj/ppa.itb $(FBDIR)/build/firmware/ppa/soc-ls$$socname && \ If you want build PPA manually with the standalone Toolchain, you could build PPA image with the command "./build prod rdb-fit dbg ls1043". Please deploy PPA image at 0x60400000 on NOR flash(the current bank).   L1/L2 cache error detection and correction EDAC feature verification   NXP LSDK 19.03 devel localhost login: root Password: Last login: Fri May 17 00:11:26 UTC 2019 on ttyS0 Welcome to NXP LSDK 19.03 devel (GNU/Linux 4.14.16-dirty aarch64)    * Support:        https://www.nxp.com/lsdk  * Documentation:  https://lsdk.github.io setting 31 rows and 111 columns root@localhost:~# ls /sys/devices/system/edac/cpu_cache/ cpu_cache0  l1_ce_sw_inject  l1_ue_sw_inject  l2_ue_hw_inject  log_ce  panic_on_ue device      l1_ue_hw_inject  l2_ce_sw_inject  l2_ue_sw_inject  log_ue  poll_msec   root@localhost:~#  echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [   74.831916] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [   74.831916] ' echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject^C root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject [   80.192338] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [   80.192338] ' root@localhost:~# root@localhost:~# root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [  109.647966] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  109.647966] ' [  109.659012] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  109.659012] '   root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_sw_inject root@localhost:~# [  136.271980] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  136.271980] ' [  136.283027] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  136.283027] '   root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l1_ue_hw_inject [  157.352298] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 2 [  157.352298] ' root@localhost:~# echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_sw_inject root@localhost:~# [  183.375947] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  183.375947] '   root@localhost:~#  echo 1 > /sys/devices/system/edac/cpu_cache/l2_ue_hw_inject [  186.928679] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  186.928679] ' root@localhost:~# [  191.055944] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  191.055944] '   root@localhost:~# dmesg | grep EDAC [    1.819380] EDAC MC: Ver: 3.0.0 [    3.423554] EDAC DEVICE0: Giving out device to module edac-a53 controller cortex_edac_l1_l2: DEV edac-a53 (POLLED) [   74.831898] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [   74.831910] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [   74.831916] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [   80.192307] EDAC cortex_edac_l1_l2: CPU 1 L1-D Data RAM error(s) detected [   80.192326] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000089000002) [   80.192338] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  109.647919] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [  109.647938] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [  109.647942] EDAC cortex_edac_l1_l2: CPU 1 L1-I Tag RAM error(s) detected [  109.647955] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000080000000) [  109.647966] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  109.659012] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  136.271933] EDAC cortex_edac_l1_l2: CPU 0 L1-I Tag RAM error(s) detected [  136.271951] EDAC cortex_edac_l1_l2: CPU 0 L1 fatal error(s) detected (0x8000000080000000) [  136.271956] EDAC cortex_edac_l1_l2: CPU 1 L1-I Tag RAM error(s) detected [  136.271969] EDAC cortex_edac_l1_l2: CPU 1 L1 fatal error(s) detected (0x8000000080000000) [  136.271980] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 0 [  136.283027] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 1 [  157.352268] EDAC cortex_edac_l1_l2: CPU 2 L1-D Data RAM error(s) detected [  157.352287] EDAC cortex_edac_l1_l2: CPU 2 L1 fatal error(s) detected (0x8000000089180002) [  157.352298] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L1 'Fatal error(s) on CPU 2 [  183.375931] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x8000000080000000) [  183.375947] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  186.928662] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910c4058) [  186.928679] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 [  191.055928] EDAC cortex_edac_l1_l2: CPU 0 L2 fatal error(s) detected (0x80000000910d0868) [  191.055944] EDAC DEVICE0: UE: cortex_edac_l1_l2 instance: cpu_cache0 block: L2 'Fatal error(s) on CPU 0 root@localhost:~# Re: EDAC L1 and L2 cache error detection and correction on LS1043 Hello All, I am stuck on how to inject cache related faults in the system (Arm r52). I can see there is a way to inject faults in CRS using EIM, is there something similar to inject faults in Cohorts as well? If yes, please can you tell me on how to test by injecting cache fault and checking the output.
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eIQ Heterogenous Demo This demo shows a low power smart door running eIQ heterogeneously on i.MX8MMini: Cortex A53 performs face recognition using eIQ OpenCV Cortex M4 performs Key Word Spotting using eIQ CMSIS-NN The demo application is build around the Django framework running on the board. It has two main usage scenarios: The first one is to manage users and inspect the access logs through a dashboard. This dashboard is accesses from a web browser on the host PC. The second use case is the smart door application itself running on the board. The scenario is the following: Cortex A cores and connected peripherals stay in low power mode. Cortex M is active, waiting for the Key Word ‘GO’. When the word is detected, Cortex M sends an MU interrupt to Cortex A and the system wakes up. Now Cortex A performs face recognition and allows access for registered users. In addition to face recognition, the MPUs are able to run a Django server to manage the user’s database, a QT5 application for the graphical interface and perform training on the edge. The algorithm for face recognition running on Cortex A and the one for key word spotting running on Cortex M are both implemented using eIQ. For the MPU eIQ support is integrated in Yocto. For the MCU the support was ported to i.MX8 from the MCU Expresso SDK for RT for the purpose of this demo. Software Environment Ubuntu 16 host PC SD card image with Yocto BSP 4.14.98/sumo 2.0.0 GA for i.MX8MMini platform with eIQ OpenCV AND eIQ heterogenus demo. See detailed steps in Build Yocto Image section CMSIS-NN MCUXpresso SDK version 2.6.0 for i.MX8MMini (SDK_2.6.0_EVK-MIMX8MM-ARMGCC). See detailed build steps in Build Cortex M4 executable section. HW Environment i.MX 8MMini Kit Touch screen display (preferred resolution 1920x1080). Tested with HDMI connection to the board. NOTE: if the display does not support touch, a mouse can be connected to the board and used instead MIPI-CSI Camera module Microphone: Synaptics CONEXANT AudioSmart® DS20921 Ribbon, 4 female-female wires and 60 pins connector to connect mic to board Optional: headphones (used to test recording on M4 - everything recorded by the mic will be played to the headphones). Host PC for remote access to the demo application (used Chrome browser) NOTE: The board and the host PC should be in the same network to communicate. Build Yocto image: Step 1 – Project initialization: $: mkdir imx-linux-bsp $: cd imx-linux-bsp-bsp $: repo init -u https://source.codeaurora.org/external/imx/imx-manifest -b imx-linux-sumo -m imx-4.14.98-2.0.0_machinelearning.xml $: repo sync Step 2 - Setup Project build: $: MACHINE=imx8mmevk DISTRO=fsl-imx-xwayland source ./fsl-setup-release.sh -b bld-xwayland Step 3 – Download project layer in ${BSPDIR}/sources/: $: git clone https://source.codeaurora.org/external/imxsupport/meta-eiq-heterogenous Step 4 – Add project layer into bblayers: Add the following line into ${BSPDIR}/sources/base/conf/bblayers.conf: BBLAYERS += " ${BSPDIR}/sources/meta-eiq-heterogenous " Step 5 – Enable eIQ and other dependencies. Add the following lines into conf/local.conf: EXTRA_IMAGE_FEATURES = " dev-pkgs debug-tweaks tools-debug \ tools-sdk ssh-server-openssh" IMAGE_INSTALL_append = " net-tools iputils dhcpcd which gzip \ python3 python3-pip wget cmake gtest \ git zlib patchelf nano grep vim tmux \ swig tar unzip parted \ e2fsprogs e2fsprogs-resize2fs" IMAGE_INSTALL_append = " python3-pytz python3-django-cors-headers" IMAGE_INSTALL_append = " opencv python3-opencv" PACKAGECONFIG_append_pn-opencv_mx8 = " dnn python3 qt5 jasper \ openmp test neon" PACKAGECONFIG_remove_pn-opencv_mx8 = "opencl" TOOLCHAIN_HOST_TASK_append = " nativesdk-cmake nativesdk-make" PREFERRED_VERSION_opencv = "4.0.1%" PREFERRED_VERSION_python3-django = "2.1%" IMAGE_ROOTFS_EXTRA_SPACE = "20971520" Step 6 – Bake the image: $: bitbake image-eiq-hetero Build Cortex M4 executable Download MCUXpresso SDK version 2.6.0 for i.MX8MMini (SDK_2.6.0_EVK-MIMX8MM-ARMGCC) OS: Linux, Toolchain: GCC ARM Embedded Components: Amazon-FreeRTOS, CMSIS DSP Library, multicore SDK Version: 2.6.0 (2019-06-14) SDK Tag: REL_2.6.0_REL10_RFP_RC3_4 Download CMIS NN and copy "CMSIS\NN" folder to "$MCUXpressoSDK_ROOT\CMSIS" Got to "$MCUXpressoSDK_ROOT\boards\evkmimx8mm\demo_apps\" Get M4 app from CAF: git clone https://source.codeaurora.org/external/imxsupport/eiq-heterogenous-cortexm4 [Win]: Open ARM GCC console and go to "$MCUXpressoSDK_ROOT\boards\evkmimx8mm\demo_apps\eiq-heterogenous-cortexm4\armgcc\" [Win]: Call "build_ddr_release.bat" to obtain "eiq-kws.bin". Deploy "eiq-kws.bin" to the Yocto image on the boot partition. Prepare the Demo 1.  Connect 12V power supply to the board, switch SW101 to power on the board 2.  Connect a USB cable between the host PC and the J901 USB port on the target board. 3.  Open two serial terminals for A53 core and M4 core with the following settings:     - 115200 baud rate     - 8 data bits     - No parity     - One stop bit     - No flow control 4. Connect display to the board (used 1920x1080 HDMI display connected to the board with an IMX-MIPI-HDMI adapter). NOTE: depending on the display, you might want to change the config in "/etc/xdg/weston/weston.ini". The demo was tested by uncommenting the following section in this file: [output] name=HDMI-A-1 mode=1920x1080@60 transform=90 5.Connect MIPI-CSI camera to the board. 6. Connect Synaptics microphone to the board using a 60 pins connector with a ribbon. SAI3 is used for record and playback on Cortex M4. The following pins are used: Pin 44 (connector) <-> I2S_TX_Data1 (mic board) Pin 43 (connector) <-> I2S_TX_LRCLK (mic board) Pin 41 (connector) <-> I2S_TX_CLK (mic board) Pin 60 (connector) <-> GND (mic board) 7. Using U-Boot command to run the demo.bin file. For details, please refer to "Getting Started with MCUXpresso SDK for i.MX 8M Mini.pdf". 8.  After running the demo.bin, using the "boot" command to boot the kernel on the A core terminal; 9.  After the kernel is boot, using "root" to login. 10.  After login, make sure imx_rpmsg_pingpong kernel module is inserted (lsmod) or insert it (modprobe imx_rpmsg_pingpong). Run the Demo Start Key Word Spotting on Cortex M4: Stop in u-boot and run the eiq-kws.bin executable in DDR: u-boot=>fatload mmc 0 0x80000000 eiq-kws.bin u-boot=>dcache flush u-boot=>bootaux 0x80000000 u-boot=>boot After the boot process succeeds, the ARM Cortex-M4 terminal displays the following information: RPMSG Ping-Pong FreeRTOS RTOS API Demo... RPMSG Share Base Addr is 0xb8000000 During boot the Kernel,the ARM Cortex-M4 terminal displays the following information: Link is up! Nameservice announce sent. Start Face Recognition on Cortex-A: Insert updated rpmsg driver: $: modprobe imx_rpmsg_pingpong After the Linux RPMsg pingpong module was installed, the ARM Cortex-M4 terminal displays the following information: Looping forever... Waiting for ping... Sending pong... 96% go First time only: $: cd ~/eiq-heterogenous-cortexa $: python3 wrap_migrate.py $: python3 wrap_createsuperuser.py Start: $: cd ~/eiq-heterogenous-cortexa $: python3 manage.py runserver 0.0.0.0:8000 --noreload & $: /opt/src/bin/src NOTE: the first instruction will start the django server, the second instruction will show the pin-pad on the display. Browser access from HOST PC: - http://$BOARD_IP:8000/dashboard/😞 Dashboard that facilitates managing users and view access logs - http://$BOARD_IP:8000/admin/: manage users database   i.MX 8
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系统控制器固件 101 [中文翻译版] 见附件   原文链接: https://community.nxp.com/docs/DOC-342654  i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus
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Security Features on i.MX-RT
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Smart Amp Software_Connects China Smart Amp software enhancement integrated with smart amplifier to provide optimal end-to-end solution such as voice experience, audio capture and speech assist for mobile and IoT applications. Smart Amp software enhancement integrated with smart amplifier to provide optimal end-to-end solution such as voice experience, audio capture and speech assist for mobile and IoT applications.
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Murata: Introducing Murata Wi-Fi IBT Connectivity Modules for NXP i.MX & RT Platform Introducing Murata Wi-Fi IBT Connectivity Modules for NXP i.MX & RT Platform. Introducing Murata Wi-Fi IBT Connectivity Modules for NXP i.MX & RT Platform. i.MX Applications Processors Interface & Connectivity Re: Murata: Introducing Murata Wi-Fi IBT Connectivity Modules for NXP i.MX & RT Platform Murata has partnered with NXP Semiconductors N.V., Cypress Semiconductor Corporation, and Embedded Artists tellsubway.com AB to offer a complete Wi-Fi and Bluetooth connectivity environment for building world class Internet-connected products.
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Example MPC5777C-eTPU_GPIO_test GHS714 ******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ******************************************************************************** ******************************************************************************** * Detailed Description: * A simple example configures eTPU engine B channels 0/1 for GPO/GPI. It is * needed to connect these pins by wire. Output wave is generated by eTPU GPIO * output function and inputs are read by fs_etpu_gpio_input_immed function * latching just current pin state. Pin history is displayed in ISR. * * Note: It is needed to configure IGF module, otherwise inputs does not pass * to eTPU module. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  ETPUB0 (PortR P25-1) --> ETPUB1 (PortR P25-0) by wire * ******************************************************************************** Re: Example MPC5777C-eTPU_GPIO_test GHS714 Hi, please create new thread here on the community space or new case according to following procedure: https://community.nxp.com/docs/DOC-329745 Re: Example MPC5777C-eTPU_GPIO_test GHS714 I tried with 2 cases: - The ETPUA_15 channel with SDADC2 - The ETPUA_9 channel with SDADC1. The pinstate always be 0. Re: Example MPC5777C-eTPU_GPIO_test GHS714 Sorry, the ETPU channel is ETPUA_15 Re: Example MPC5777C-eTPU_GPIO_test GHS714 Hello David, As I know, the input of ETPU channel can be connected from the SDADC valid data flag output or the external pad, we use the SIU_SDETPUA, SIU_SDETPUB, SIU_SDETPUC to choose the connection .You can see the below image: - I use ETPUA channel 9:       + In the case 1, ETPUA_9 is connected to the external pad, the pinstate returned by fs_etpu_gpio_pin_history is correct as expected.       + In the case 2,  ETPUA_9 is connected to the SDADC1 data valid flag output, the pinstate returned by fs_etpu_gpio_pin_history always be 0 even though the SDADC1 Conversion Data Valid Event is enabled(CDVEE bit of SDADC_RSER is 1) and Converted Data Valid Flag is 1(CDVF bit of SDADC_SFR is 1). This is wrong. I don't know why. - The difference between these 2 cases is just SIU_SDETPUA configuraion. Do you know why? Regards, Tam
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Murata:推出适用于 NXP i.MX 和 RT 平台的 Murata Wi-Fi IBT 连接模块 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 推出适用于 NXP i.MX 和 RT 平台的 Murata Wi-Fi IBT 连接模块。 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 推出适用于 NXP i.MX 和 RT 平台的 Murata Wi-Fi IBT 连接模块。 i.MX 应用处理器 接口和连接 回复:Murata:推出适用于 NXP i.MX 和 RT 平台的 Murata Wi-Fi IBT 连接模块 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> Murata 已与 NXP Semiconductors NV、Cypress Semiconductor Corporation 和 Embedded Artists 合作tellsubway.comAB 提供完整的 Wi-Fi 和蓝牙连接环境,用于构建世界一流的互联网连接产品。
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MRFX Design Challenge Winners! NXP received a number of creative submissions over the course of the MRFX Design Challenge. We appreciate the enthusiasm from the community as designers were hard at work on their RF projects. Now is the moment everyone's been waiting for as NXP proclaims the MRFX Design Challenge winners. First Place Winner  Russell Kendrick | Bio + Full Project Description Project Video: MRFX1K80H 50 MHz Project Brief This amplifier is intended to be driven with a modern transceiver with 100 watts output on 50 MHz. To protect the MRFX1K80H from overdrive a series of RF pads are used to reduce the input to the proper level. The input matching is accomplished by using a 9:1 conventional RF transformer formed on an Amidon BN 61-202 core. An 82 nH inductance is in series with the high impedance winding of the transformer. This arrangement yielded an input match of 1.3:1 SWR over the entire 6-meter Amateur band when measured without the pads. Shunt gate resistance is used to prevent oscillation at low frequencies. This is the same approach used in the 27 MHz test circuit from NXP. Bias will be supplied by a DAC driven by the microcontroller that will manage the finished amplifier Second Place Winner        Floris Roosen | Bio                                                                         Project Video: Roosen Single-Ended Broadband (87-110 MHz) RF Design         Third Place Winner Mike Mysliwiec | Bio Project Video: 2xMRFX1K80H 1.8-54 MHz HF Amplifier   Overview  NXP is hosting an RF power amplifier design contest. Applicants will record a video of their power amplifier/demo using NXP’s new 65V LDMOS 1800 W RF Power transistor, MRFX1K80H The contest is open to students, professional engineers, companies or individuals Key Dates Contest kick-off: October 30, 2017 Submit a video (3-5 minutes in length) no later than Friday, January 26, 2018, by sending a link to any video website, such as YouTube, YouKu or others to [email protected] Results will be announced on Monday, February 12, 2018 Prizes • 1st prize: $3,000 cash award + 15 MRFX1K80H samples. Showcase designer bio and video in an NXP blog • 2nd prize: $1,000 cash award + 10 MRFX1K80H samples • 3rd prize: $500 cash award + 10 MRFX1K80H samples The prize amounts are before tax All accepted videos will be posted on www.nxp.com/videos  Judging Criteria How to enter the competition Please click on the link below for the latest details and to access the MRFX Design Challenge page www.nxp.com/MRFXdesign  Communications Infrastructure
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How to generate duty cycle of PWM_X for eFlexPWM module The documentation talks about the PWM_nX signal, gives the register setting to set up the duty cycle of PWM_X, and tricks to control the timing of PWM_nX, and the restriction for PWM_X.
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NXP Tech Session - Democratizing the Establishment of Secure Connections View the Webinar Recording View the Webinar Recording QN
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Kinetis - M Two - Phase Power Meter Reference Design (DRM149) On NXP website we had provide an application note " Kinetis-M Two-Phase Power Meter Reference Design" which can been found here: http://www.nxp.com/docs/en/application-note/DRM149.pdf  This is really a quite useful solution for 2-Phase Power Meter design. From the schematic, there has a LCD display. Many customer sent email to ask for the datasheet of this LCD display(GDH-1247WP). Yes agreed, it is really difficult to find it. ( Even from the google.) I am attaching the data sheet for the segment LCD here for customer to make reference.
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S32 Design Studio for Power Architecture 2017.R1 - Update 11 available       Product Release Announcement Automotive Microcontrollers and Processors S32 Design Studio for Power Architecture 2017.R1 Update 11          What is new? S32 SDK for Power Architecture RTM 3.0.0 supporting  S32R274, S32R372, MPC574x-B-C-G, MPC574x-P, MPC574x-R and MPC577x-B-E-C (see the S32 SDK release notes) Integrated Radar SDK RTM 1.2.1 (see the Radar SDK release notes) This is a cumulative update - it includes all of the content of previous updates (Update 1, Update 2, Update 3, Update 4, Updates 5 and 6, Update 7, Update 8, Update 9, Update 10  ). Installation instructions The update is available for online installation (via S32DS Eclipse Updater) or offline installation (direct download link)  installation:  go to menu "Help" -> "Install New Software..." dialog  select predefined update site "S32DesignStudio - http://www.nxp.com/lgfiles/updates/Eclipse/S32DS_POWER_2017.R1/updatesite" select all available items and click "Next" button offline installation:   go to S32 Design Studio for Power product page -> Downloads section or use direct link to download the update archive zip file  Start S32DS and go to "Help" -> "Install New Software..." Add a new "Archive" repository and browse to select the downloaded update archive zip file you downloaded in the previous step Select all available items and click "Next" button.   This will start the update installation process. General SDKs
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eIQ Sample Apps - Object Recognition using OpenCV DNN This Lab 3 explains how to get started with OpenCV DNN applications demos on i.MX8 board using eIQ ™ ML Software Development Environment. eIQ Sample Apps - Overview eIQ Sample Apps - Introduction Get the source code available on code aurora: OpenCV DNN example - File-Based and MIPI Camera OpenCV Inference The OpenCV offers a unitary solution for both neural network inference (DNN module) and classic machine learning algorithms (ML module). Moreover, it includes many computer vision functions, making it easier to build complex machine learning applications in a short amount of time and without having dependencies on other libraries. The OpenCV DNN model is basically an inference engine. It does not aim to provide any model training capabilities. For training, one should use dedicated solutions, such as machine learning frameworks. The inference engine from OpenCV supports a wide set of input model formats: TensorFlow, Caffe, Torch/PyTorch. Comparison with Arm NN Arm NN is a library deeply focused on neural networks. It offers acceleration for Arm Neon, while Vivante GPUs are not currently supported. Arm NN does not support classical non-neural machine learning algorithms. OpenCV is a more complex library focused on computer vision. Besides image and vision specific algorithms, it offers support for neural network machine learning, but also for traditional non-neural machine learning algorithms. OpenCV is the best choice in case your application needs a neural network inference engine, but also other computer vision functionalities. Setting Up the Board Step 1 - Create the following folders and grant them permissions as it follows: root@imx8mmevk:# mkdir -p /opt/opencv/model root@imx8mmevk:# mkdir -p /opt/opencv/media root@imx8mmevk:# chmod 777 /opt/opencv Step 2 - To easily deploy the demos to the board, get the boards IP address using ifconfig command, then set the IMX_INET_ADDR environment variable as it follows: $ export IMX_INET_ADDR= Step 3 - In the target device, export the required variables: root@imx8mmevk:~# export LD_LIBRARY_PATH=/usr/local/lib root@imx8mmevk:~# export PYTHONPATH=/usr/local/lib/python3.5/site-packages/   Setting Up the Host Step 1 - Download the application from eIQ Sample Apps. Step 2 - Get the models and dataset. The following command-line creates the needed folder structure for the demos and retrieves all needed data and model files for the demo: $ mkdir -p model $ wget -qN https://github.com/diegohdorta/models/raw/master/caffe/MobileNetSSD_deploy.caffemodel -P model/ $ wget -qN https://github.com/diegohdorta/models/raw/master/caffe/MobileNetSSD_deploy.prototxt -P model/   Step 3 - Deploy the built files to the board: $ scp -r src/* model/ media/ root@${IMX_INET_ADDR}:/opt/opencv OpenCV DNN Applications This application was based on: SSD: Single Shot MultiBox Detector. Caffe SSD Implementation. 1 - OpenCV DNN example: File-Based The folder structure must be equal to: ├── file.py ├── camera.py ├── media └── ... ├── model │├── MobileNetSSD_deploy.caffemodel │└── MobileNetSSD_deploy.prototxt This example runs a single picture for example, but you pass as many pictures as you want and save them inside media/ folder. The application tries to recognize all the objects in the picture. Step 1 - For copying new images to the media/ folder: root@imx8mmevk:/opt/opencv/media# cp .   Step 2 - Run the example image: root@imx8mmevk:/opt/opencv# ./file.py  NOTE: If GPU is available, the example shows: [INFO:0] Initialize OpenCL runtime This demo runs the inference using a Caffe model to recognize a few type of objects for all the images inside the media/ folder. It includes labels for each recognized object in the input images. The processed images are available in the media-labeled/ folder. See before and after labeling: Step 3 - Display the labeled image with the following line: root@imx8mmevk:/opt/opencv/media-labeled# gst-launch-1.0 filesrc location= ! jpegdec ! imagefreeze ! autovideosink 2 - OpenCV DNN example: MIPI Camera This example is the same as above, except that it uses a camera input. It enables the MIPI camera and runs an inference on each captured frame, then displays it in a window interface in real time: root@imx8mmevk:/opt/opencv# ./camera.py 3 - OpenCV DNN example: MIPI Camera improved This example differs from the above due the additional support of GStreamer applied to it. Using the Leaky Bucket algorithm idea, the GStreamer pipeline enables the camera to continue performing its own thread (bucket overflow when full), even if the frame was not processed by the inference thread (bucket water capacity). As a result of this Leaky Bucket algorithm, this demo has smooth camera video at the expense of having some frames dropped in the inference process. root@imx8mmevk:/opt/opencv# ./camera_improved.py Go to the eIQ Sample Apps - Face Recognition using TF Lite. i.MX 8 Re: eIQ Sample Apps - Object Recognition using OpenCV DNN Hi coindu‌, As vanessamaegima‌ said before, we do not have a validated solution for video file source yet, but I can anticipate that using a video file directly on OpenCV VideoCapture property will return the worst possible results. So please, try applying the video file to a GStreamer pipeline, such as the example below: filesrc location=video_device.mp4 typefind=true ! decodebin !  imxvideoconvert_g2d ! video/x-raw,format=RGBA,width={},height={} ! videoconvert !  appsink sync=false BR, Marco Re: eIQ Sample Apps - Object Recognition using OpenCV DNN I reference the camera_improved.py demo, use video to instead of the v4l2 as input .   The fps of video is 15, it means the display on the screen time is 0.067sec. But it will cost 0.6sec to parse one frame,which frame is 480x272. So object recognition block diagram will be delayed than video. I want to parse the 10th frame when the first frame of the video is played. But this method cannot move to a certain frame. Re: eIQ Sample Apps - Object Recognition using OpenCV DNN Hi coindu‌, We provided a demo with improved performance in step 3 (3 - OpenCV DNN example: MIPI Camera improved). The same approach was not validated with video input yet. Could you please give it a try and see if it helps? marcofranchi‌, FYI. Thanks, Vanessa Re: eIQ Sample Apps - Object Recognition using OpenCV DNN hi:     I try to test this example with video.However, I found that the time for dnn to parse a frame is almost close to the display time of 10 frames of video. def dnn_parse(nn,frame,multipe=1):     height,width,color_lane=frame.shape     if multipe != 1:         height = int(height*multipe)         width = int(width*multipe)         print "h:{}w:{}".format(height,width)         frame=opencv.resize(frame,(height,width))     start_time=time.time()    blob = opencv.dnn.blobFromImage(frame,0.009718,(height,width),127.5)     nn.setInput(blob)    det=nn.forward()    end_time=time.time()    print "height{} width{} time{}".format(height,width,end_time-start_time) h:136w:240height136 width240 time0.264429092407height272 width480 time0.620328903198h:544w:960height544 width960 time2.25029802322   Then consider directly analyzing N * k frames when dnn analysis (k =, 1, 2, 3 ...). But found that opencv does not support frame skipping and calculating the total number of video frames. #!/usr/bin/env python # -*- coding: utf-8 -*- import cv2 as opencv import time if __name__ == "__main__": cap = opencv.VideoCapture('car.mp4') opencv.namedWindow("appFrame") frame_count = cap.get(opencv.CAP_PROP_FRAME_COUNT) print "frame_count.{}".format(frame_count) cap.set(opencv.CAP_PROP_POS_FRAMES,200) ret,frame = cap.read() opencv.imshow("appFrame",frame) opencv.waitKey(0) opencv.destroyAllWindows() cap.release() (python:4431): GStreamer-CRITICAL **: gst_query_set_position: assertion 'format == g_value_get_enum (gst_structure_id_get_value (s, GST_QUARK (FORMAT)))' failed Using Wayland-EGL Using the 'xdg-shell-v6' shell integration frame_count.-1.0 WARN: h264bsdDecodeSeiParameters not valid How to solve this problem? Re: eIQ Sample Apps - Object Recognition using OpenCV DNN Thanks man.. And one more thing, does Opencv perform inference on GPU or CPU? Re: eIQ Sample Apps - Object Recognition using OpenCV DNN Hi Dinesh, Go to the repository and click on "summary", below it will have a clone link so you can download the repository using git tool: $ git clone https://source.codeaurora.org/external/imxsupport/eiq_sample_apps Cloning into 'eiq_sample_apps'... remote: Counting objects: 87, done. remote: Compressing objects: 100% (79/79), done. remote: Total 87 (delta 30), reused 26 (delta 4) Unpacking objects: 100% (87/87), done. $ cd eiq_sample_apps/ Hope this helps Thanks, Diego Re: eIQ Sample Apps - Object Recognition using OpenCV DNN Hey hi diegodorta  how to download the source code to setup host machine from here..
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Example MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614 ******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in internal DMA TCD RAM (user must choose it in the option at the end of * main function). * EIM (Error Injection Module) is used to simulate a multi-bit or single-bit * ECC error in DMA TCD RAM (Peripheral RAM). * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ******************************************************************************** ******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in internal DMA TCD RAM (user must choose it in the option at the end of * main function). * EIM (Error Injection Module) is used to simulate a multi-bit or single-bit * ECC error in DMA TCD RAM (Peripheral RAM). * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ******************************************************************************** Re: Example MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614 Hello David ,       1b+2b_PERRAM_ECC_error_injection doesn't work in my main function,PR_CE and PR_UCE of MEMU_ERR_FLAG register are always zero,my chip is SPC5744PFK1AMLQ9,the 1b+2b_PERRAM_ECC_error_injection code that injected into the main function is as the follows pictures:       Thanks for your help!! Re: Example MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614 I am sorry but I don't understand you. Could you clarify what exactly does not work for you? Thanks Re: Example MPC5744P 1b+2b_PERRAM_ECC_error_injection GHS614 Hello, I encountered a problem in the process of testing 5744: MEMU_PERIPH_RAM_CERR,MEMU_PERIPH_RAM_UNCERR injection failed to make the MEMU_ERR_FLAG register PR_CE,PR_UCE set, the test code is downloaded from the NXP website. At the end of the main function injection, the code is as follows: #define EIM_EICHEN_DMA_memory_0 0x80000000u // must be somewhere in DMA TCD area i.e. 0xFC0A1000-0xFC0A13FE #define Injected_ECC_error_address 0xFC0A1000u void Generate_1b_ECC_error_in_DMA_TCD(void) { register vuint32_t test_read = 0u; //printf("ECC 1b error injected into RAM\r\n"); /* invert 1 LSB bits to create non-correctable data error */ EIM.EICHD_Word1.R = 0x00000001u; /* PRAMC_0 channel error injection enable */ EIM.EICHEN.R = EIM_EICHEN_DMA_memory_0; /* global error injection enable */ EIM.EIMCR.R = 1u; /* error caused by read (it should set MCSR[MAV, LD, BUS_DRERR]) */ test_read = *(unsigned int*) Injected_ECC_error_address; } void Generate_2b_ECC_error_in_DMA_TCD_duplicate(void) { register vuint32_t test_read = 0u; //printf("ECC 2b error injected into RAM\r\n"); /* invert 2 LSB bits to create non-correctable data error */ EIM.EICHD_Word1.R = 0x00000003u; /* PRAMC_0 channel error injection enable */ EIM.EICHEN.R = EIM_EICHEN_DMA_memory_0; /* global error injection enable */ EIM.EIMCR.R = 1u; /* error caused by read (it should set MCSR[MAV, LD, BUS_DRERR]) */ test_read = *(unsigned int*) Injected_ECC_error_address; } note: FLASH_RAM,SYS_RAM can use NXP Web site code to implement error_injection. Thank you very much for your help!
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Powertrain & Vehicle Dynamics: NXP’s xEV Energy Management Solutions The region expects each OEM to make and sell 12% of its output as ZEVs by 2020, large cities ban classic ICE-vehicles, car makers announce new EVs with increasing cadence. This session shall give an overview of the main forces influencing the EV market, describe the main architectural approaches and system components as well as what growth potential this has for NXP. The region expects each OEM to make and sell 12% of its output as ZEVs by 2020, large cities ban classic ICE-vehicles, car makers announce new EVs with increasing cadence. This session shall give an overview of the main forces influencing the EV market, describe the main architectural approaches and system components as well as what growth potential this has for NXP.
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opencv 3.1 supports on the mx6q board OpenCV (Open Source Computer Vision Library) is released under a BSD license and hence it’s free for both academic and commercial use. It has C++, C, Python and Java interfaces and supports Windows, Linux, Mac OS, iOS and Android. OpenCV was designed for computational efficiency and with a strong focus on real-time applications. Written in optimized C/C++, the library can take advantage of multi-core processing. Enabled with OpenCL, it can take advantage of the hardware acceleration of the underlying heterogeneous compute platform In current bsp , which supports opencv 2.4, but some customer wants to use the opencv 3.1, then one can use the morty yocto bsp to install the opencv. step 1: for how to install the package on ubuntu and how to build the environment, pls refer to the bsp user guide, for how to build the branch morty, try to use the command as below: MACHINE=imx6qsabresd source fsl-setup-release.sh -b build_qt5 -e fb step 2: for how to enable the opencv, pls add the command as below in the local.conf, the path is fsl-release-bsp/build/conf, "CORE_IMAGE_EXTRA_INSTALL += "libopencv-core-dev libopencv-highgui-dev libopencv-imgproc-dev libopencv-objdetect-dev libopencv-ml-dev" CORE_IMAGE_EXTRA_INSTALL += "opencv-apps opencv-dev python-opencv python-modules"" then build again by bitbake. then you can find the image in the fsl-release-bsp/build/tmp/deploy/images/im6qsabresd/, one can find the opencv libary when extracting the rootfs file step 3: then you can use dd command or mfgtool downloading the image file to the board and use the opencv libary file. other usage: one can install the populate_sdk to build the source code, for opencv 3.1, maybe you will find some g++ issue to fix, so just simple introduce this use the command: bitbake -c populate_sdk fsl-image-gui(for example)  then you can find the sdk install file in the fsl-release-bsp/build_x11/tmp/deploy/sdk, run the install file, set the installation file in the /opt/poky, then you can find the toolchain in the /opt/poky after install successfully.
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