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IMXRT1170-EVKB - SAI TDM Hello everyone, I'm trying to implement a SAI with TDM protocol for audio data transfer. Starting from sai_edma_tdm_record_playback without CS42448, I've changed few configurations in order to implement a loopback between SAI1_RX/TX. Links are: TX_BCLK -> RX_BCLK TX_SYNC -> RX_SYNC TX_DA0 -> RX_DA0 On an oscilloscope connected to TX_DA0, it is possible to see data sent but they are uncorrect. someone can explain to me how to correctly configure a TDM communication and what is wrong in the code below? Thanks a lot, -F AT_NONCACHEABLE_SECTION_ALIGN(static uint8_t Buffer[BUFFER_NUMBER * BUFFER_SIZE], 4); #if defined(DEMO_QUICKACCESS_SECTION_CACHEABLE) && DEMO_QUICKACCESS_SECTION_CACHEABLE AT_NONCACHEABLE_SECTION_INIT(sai_edma_handle_t txHandle); AT_NONCACHEABLE_SECTION_INIT(sai_edma_handle_t rxHandle); #else AT_QUICKACCESS_SECTION_DATA(sai_edma_handle_t txHandle); AT_QUICKACCESS_SECTION_DATA(sai_edma_handle_t rxHandle); #endif static uint32_t tx_index = 0U, rx_index = 0U; volatile uint32_t emptyBlock = BUFFER_NUMBER; edma_handle_t dmaTxHandle = {0}, dmaRxHandle = {0}; extern codec_config_t boardCodecConfig; codec_handle_t codecHandle; /******************************************************************************* * Code ******************************************************************************/ static void rx_callback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData) { if (kStatus_SAI_RxError == status) { /* Handle the error. */ } else { emptyBlock--; } } static void tx_callback(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData) { if (kStatus_SAI_TxError == status) { /* Handle the error. */ } else { emptyBlock++; } } /*! * @brief Main function */ int main(void) { sai_transfer_t xfer; edma_config_t dmaConfig = {0}; sai_transceiver_t saiConfig; BOARD_InitHardware(); PRINTF("SAI TDM record playback example started!\n\r"); /* Init DMA and create handle for DMA */ EDMA_GetDefaultConfig(&dmaConfig); #if defined(BOARD_GetEDMAConfig) BOARD_GetEDMAConfig(dmaConfig); #endif EDMA_Init(EXAMPLE_DMA, &dmaConfig); EDMA_CreateHandle(&dmaTxHandle, EXAMPLE_DMA, EXAMPLE_TX_CHANNEL); EDMA_CreateHandle(&dmaRxHandle, EXAMPLE_DMA, EXAMPLE_RX_CHANNEL); #if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX EDMA_SetChannelMux(EXAMPLE_DMA, EXAMPLE_TX_CHANNEL, EXAMPLE_SAI_TX_SOURCE); EDMA_SetChannelMux(EXAMPLE_DMA, EXAMPLE_RX_CHANNEL, EXAMPLE_SAI_RX_SOURCE); #endif #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT #if defined(EXAMPLE_DMAMUX_TX_CHANNEL) && defined(EXAMPLE_DMAMUX_RX_CHANNEL) /* Init DMAMUX */ DMAMUX_Init(EXAMPLE_DMAMUX_TX); DMAMUX_Init(EXAMPLE_DMAMUX_RX); DMAMUX_SetSource(EXAMPLE_DMAMUX_TX, EXAMPLE_DMAMUX_TX_CHANNEL, (uint8_t)EXAMPLE_SAI_TX_SOURCE); DMAMUX_EnableChannel(EXAMPLE_DMAMUX_TX, EXAMPLE_DMAMUX_TX_CHANNEL); DMAMUX_SetSource(EXAMPLE_DMAMUX_RX, EXAMPLE_DMAMUX_RX_CHANNEL, (uint8_t)EXAMPLE_SAI_RX_SOURCE); DMAMUX_EnableChannel(EXAMPLE_DMAMUX_RX, EXAMPLE_DMAMUX_RX_CHANNEL); #else /* Init DMAMUX */ DMAMUX_Init(EXAMPLE_DMAMUX); DMAMUX_SetSource(EXAMPLE_DMAMUX, EXAMPLE_TX_CHANNEL, (uint8_t)EXAMPLE_SAI_TX_SOURCE); DMAMUX_EnableChannel(EXAMPLE_DMAMUX, EXAMPLE_TX_CHANNEL); DMAMUX_SetSource(EXAMPLE_DMAMUX, EXAMPLE_RX_CHANNEL, (uint8_t)EXAMPLE_SAI_RX_SOURCE); DMAMUX_EnableChannel(EXAMPLE_DMAMUX, EXAMPLE_RX_CHANNEL); #endif #endif /* SAI init */ SAI_Init(DEMO_SAI); SAI_TransferTxCreateHandleEDMA(DEMO_SAI, &txHandle, tx_callback, NULL, &dmaTxHandle); SAI_TransferRxCreateHandleEDMA(DEMO_SAI, &rxHandle, rx_callback, NULL, &dmaRxHandle); /* TDM mode configurations */ SAI_GetTDMConfig(&saiConfig, kSAI_FrameSyncLenOneBitClk, DEMO_AUDIO_BIT_WIDTH, DEMO_AUDIO_DATA_CHANNEL, kSAI_Channel0Mask); saiConfig.frameSync.frameSyncEarly = true; saiConfig.masterSlave = kSAI_Master; SAI_TransferTxSetConfigEDMA(DEMO_SAI, &txHandle, &saiConfig); saiConfig.masterSlave = kSAI_Slave; SAI_TransferRxSetConfigEDMA(DEMO_SAI, &rxHandle, &saiConfig); /* set bit clock divider */ SAI_TxSetBitClockRate(DEMO_SAI, DEMO_AUDIO_MASTER_CLOCK, DEMO_AUDIO_SAMPLE_RATE, DEMO_AUDIO_BIT_WIDTH, DEMO_AUDIO_DATA_CHANNEL); SAI_RxSetBitClockRate(DEMO_SAI, DEMO_AUDIO_MASTER_CLOCK, DEMO_AUDIO_SAMPLE_RATE, DEMO_AUDIO_BIT_WIDTH, DEMO_AUDIO_DATA_CHANNEL); /* master clock configurations */ BOARD_MASTER_CLOCK_CONFIG(); /* CS42888 initialization */ //DEMO_InitCodec(); memset((uint8_t *)&Buffer,'5', sizeof(uint8_t) * 4096); while (1) { if (emptyBlock > 0) { xfer.data = Buffer + rx_index * BUFFER_SIZE; xfer.dataSize = BUFFER_SIZE; if (kStatus_Success == SAI_TransferReceiveEDMA(DEMO_SAI, &rxHandle, &xfer)) { rx_index++; } if (rx_index == BUFFER_NUMBER) { rx_index = 0U; } } if (emptyBlock < BUFFER_NUMBER) { xfer.data = Buffer + tx_index * BUFFER_SIZE; xfer.dataSize = BUFFER_SIZE; if (kStatus_Success == SAI_TransferSendEDMA(DEMO_SAI, &txHandle, &xfer)) { tx_index++; } if (tx_index == BUFFER_NUMBER) { tx_index = 0U; } } } } Audio(PDM | I2S | SAI) Communication & Control(I3C | I2C | SPI | FlexCAN | Ethernet | FlexIO)
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S32K142芯片如何解锁 S32K142芯片,将FSEC中SEC位置为11: /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF /* 8 bytes backdoor comparison key */ .long 0xFFFFFFFF /* */ .long 0xFFFFFFFF /* 4 bytes program flash protection bytes */ .long 0xFFFF7FFF /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */ 使用PEMicro将程序烧录进入芯片后,无法再次debug,会提示“Device is secure.Erase to unsecure?”,点击yes后会再次提示,再次点击yes后则会提示PE与设备连接错误,使用JLINK也无法与其连接。 在debug configuration中勾选“Emergency Kinetis Device Recovery by Full Chip Erase”也无法连接。 Re: S32K142芯片如何解锁 Hi@minsky 用法上是没有区别的,看你的J-LINK选择的烧录算法,例如你使用的是J-FLAHS来烧的话,步骤上会让你选择烧录算法。 阅读下这个文章的下面这个章节: 5. S32K1xx系列MCU Flash编程常见问题及注意事项 https://mp.weixin.qq.com/s?__biz=MzI0MDk0ODcxMw==&mid=2247485716&idx=1&sn=979631aa2385a4e3c7651ee75ee252b4&chksm=e9124d92de65c484f1cfec7de451958cfd5cf818c46a4f71a7d3dd8a522af229c5a18aad58ff&scene=21#wechat_redirect Re: S32K142芯片如何解锁 你好,我又使用Jlink使能CSEc key和禁用debug,编译工程后使用jlink烧录,使用jlink仍可以连接芯片并读取其内容,该功能是否仅对PE有效? Re: S32K142芯片如何解锁 Hi@minsky 这是两个问题,无论你使能或者不使能backdoor,只要你使能了CSEs和分配了key,那么都必须要先擦除key才能执行mass erase操作。所以回到你的问题上,你可以先调试是CSEC key的擦除,确保这个能先成功,最后去配置启动文件中的FSEC。从你的描述上来看,我猜测可能是拆除CSEC的时候不正确之类的。 Re: S32K142芯片如何解锁 你好,我们的产品需要开启CSEc功能,请问应该如何留后门来使禁用debug后仍能进行mass erase? 我尝试先分区,使能CSEc的key,再将FSEC中SEC位置为11后,通过LIN发送信号,在接收到LIN信号后擦除csec key,但仍然失败了,是否是因为hex文件烧录至“将FSEC中SEC位置为11”处后,后续无法烧录? Re: S32K142芯片如何解锁 Hi@minsky 首先你的设置我没看出有什么问题,导致这样问题发生的可能是下面这种情形。 例如你之前是否对该芯片做过一些分区操作,使能了CSEc的key情况。如果是的话,那么是不能直接用调试器来进行mass erase操作的,必须要使用CSEc的指令擦除CSEc key之后才能运行使用mass erase来操作MCU。 Senlent_0-1761529353422.png
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S32K1: LPUART BAUDレジスタのOSRビットがスタックしています こんにちは。 ターゲット MCU は、S32K14W-Q064 評価ボード上の S32K144W です。LPUART0 ボー レートを設定しているのですが、BAUD レジスタの下位 4 つの OSR ビットをクリアできないことに気付きました。これらのビットはリセット時にデフォルトで 1 に設定されますが、その後は書き込み/クリア可能になるはずです。上位の OSR ビットを設定またはクリアCANますが、下位 4 ビットは固定され、常に設定されており、そのレジスタに対するいかなる操作でもクリアできません。 ネタバレ (ハイライトして読む) Screenshot_RM_BAUD_OSR.png 明らかに、これにより UART の機能が制限され、適切なボー レートの選択が難しくなります。ドキュメントを何度も精査しましたが、これらのビットに対する制限や、それらをクリアまたは変更するために満たさなければならない条件についての言及は見つかりませんでした。たぶん見逃したのでしょう。 他のフォーラム投稿 2 件を見つけましたが、そこではユーザーが同じ問題 (ただし、別の部分) について言及していました。 "SO、OSR フィールド (15 と 31) に設定できるのは 16 と 32 の値のみで、他の値を設定すると 16/32 になることに気づきました。" 残念ながら解決策は見当たりません。 https://community.nxp.com/t5/Kinetis-Microcontrollers/FRDM-K82F-uart-problem/mp/845950 https://community.nxp.com/t5/Kinetis-Microcontrollers/LPUART0-baudrate/mp/792047/highlight/true#M48190 これらのビットが詰まっている理由や、変更方法について何かご意見はありますか? ご協力いただきありがとうございます! トレバー Re: S32K1: LPUART BAUD register OSR bits stuck こんにちは、トレバーさん。 情報をいただきありがとうございます。 OSRビットを個別にクリアできないことにはこれまで気付いていませんでしたが、RTD のBAUDレジスタへの書き込みも一度に行われることがわかりました。 よろしくお願いいたします ロビン Re: S32K1: LPUART BAUD register OSR bits stuck こんにちは、ロビン。 私は S32K1 RTD を使用していません。UART を LPUART レジスタで直接構成しています。 明確に言うと、最初に OSR ビットと SBR ビットをクリアし (LPUART_BAUD_OSR_MASK と LPUART_BAUD_SBR_MASK を使用)、次に必要なビットを設定して (LPUART_BAUD_OSR(x) と LPUART_BAUD_SBR(x) を使用)、必要なボー レートを取得しようとしていました。重要なのは、OSR ビットをすべてクリアすると、オーバーサンプリング比が 16 になり、下位 4 ビットが設定されたデフォルトと同じになることです。リファレンスマニュアルにはこのように書かれていますが、OSR ビットをクリアすると何が起こるのかは十分に説明されていないようです。 Screenshot_RM_OSR.png 私が理解できなかったのは、OSR ビットをすべてクリアすると、ハードウェアはそれをオーバーサンプリング比 16 を使用していると解釈するのではなく、下位 4 ビットを文字通り 1 に戻し、デフォルト設定に戻すということです。SO、最初にそれらのビットをマスクしてクリアし、次に必要なビットを設定するという一般的なパターンは使用できません。代わりに、すべてのビット グループで必要な値を使用して、BAUD レジスタを一度に設定する必要があります。 SO、これを変更することで: IP_LPUART0->BAUD &= ~( LPUART_BAUD_OSR_MASK ); IP_LPUART0->BAUD |= ( LPUART_BAUD_OSR(10u) ); ... これに対して: IP_LPUART0->BAUD = ( LPUART_BAUD_OSR(10u) | ... ); 期待通りに動作しているようです。 ご協力ありがとうございました。 よろしくお願いいたします。 トレバー Re: S32K1: LPUART BAUD register OSR bits stuck ハイ BAUD[BOTHEDGE]を設定しましたか?S32K1 RTD を使用している場合は、以下を参照して設定する必要があります。 BAUD[OSR][BOTHEDGE] Lpuart_Uart_Ip_SetUp_Baudrate RTD.png よろしくお願いします、 ロビン --------------------------------------------------------------------------------- 注記: - この投稿があなたの質問への回答である場合は、「解決策として承認」ボタンをクリックしてください。ありがとう! - Threadは最後の投稿から7週間フォローされます。それ以降の返信は無視されます。 後ほど関連する質問がある場合は、新しいThreadを開いて、閉じたThreadを参照してください。 ---------------------------------------------------------------------------------
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Does size of air bubble affect MPXV5010GC7U pressure messurement I've replaced the water in the dogie squeaker with 100% silicon oil with a small air bubble in a 4mm tube into the MPXV5010GC7U sensor. Will the amount of air affect the sensor output?  Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Does a smaller initial air bubble between the 100% Silicon Oil and the sensor increase or decrease the output? The size of the air bubble does not seem to change while the readings are decreasing. Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Air bubbles do indeed affect the output. The phenomenon of slow decline is very likely caused by air bubble compression or slow pressure relief in the liquid system, rather than a fault of the sensor itself. Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Since my original post, I've disassembled the housing and found a massive air bubble at the top of the squeaker. I've redesigned the housing for a new filling technique that insures that there is no air left in the squeaker and only the air bubble to the sensor. When I started up, everything look fine when I applied 200 grams calibration weight to the sensor. However, the readout from my Android Nano decreased from '0800' to no reading (reading is below the cutoff) over several minutes. What could be the problem? Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Allow me to rephrase...how will the size of the air bubble affect the output? Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Hi: Yes, the air in the tube will affect the sensor‘s output you know the MPXV5010GC7U is a pressure sensor designed to gauge pressure.  Re: Does size of air bubble affect MPXV5010GC7U pressure messurement Another MPXV5010GC7U should be used to test for comparison. Re: Does size of air bubble affect MPXV5010GC7U pressure messurement a new sensor to test again Are referring to another MPXV5010GC7U or a different sensor?
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Design Studio v3.6.4 - 如何添加 S32 SDK RTM v4.0.2? 您好, 我是 Windows 11 上 S32 Design Studio 的新用户。 我成功安装了 S32 Design Studio v3.6.4,并通过帮助 → S32DS 扩展和更新添加了一些更新。但是,SDK 没有更新。因此,我手动下载并安装了 S32SDK_S32K1xx_RTM_4.0.2.exe (S32 SDK RTM v4.0.2)。 在 Design Studio 中创建了一个新的 S32 应用程序项目后,我发现 .mex文件丢失,代码配置器图标不可见。因此,我无法打开代码配置器来配置 GPIO 或其他外设。 我的目标是安装 RTM v4.0.2,以便使用 S32K144 的代码配置器生成简单的程序 C 代码(非 AUTOSAR 风格)。我不需要 RTD 更新。 我该如何解决这个问题? 谢谢! Re: Design Studio v3.6.4 - How to add S32 SDK RTM v4.0.2 ? 嗨,VaneB,感谢您的回复。我已卸载 DS v3.6.4,并安装了 DS v3.4。在帮助 - 扩展和更新中,我安装了 SDK RTM v4.0.3。 Re: Design Studio v3.6.4 - How to add S32 SDK RTM v4.0.2 ? 你好@TLHK S32SDK_S32K1xx_RTM_4.0.2 与 S32 Design Studio v3.6.4 不兼容。该 SDK 最初是作为 S32 Design Studio v3.4 的更新提供的。 要使用它,请下载 S32K1xx Service Pack 1 for S32DS v3.4,并通过 S32DS 扩展和更新将其安装为新的更新站点。 为确保功能正常,请务必下载并使用相应的集成开发环境版本。 BR、VaneB
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如何在 imx8mm 上保持从 uboot 到内核的徽标。 当 Uboot 启动时,我可以在屏幕上看到徽标图片,但是在 " 启动内核 " 之后屏幕会变黑 i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: How to keep logo from uboot to kernel on imx8mm. 我使用的是内核 6.6.52 和 uboot v2024.04。我有 variscite 的产品,所以我使用它们的树枝。 Re: How to keep logo from uboot to kernel on imx8mm. 感谢@topphysician分享您的解决方案。我将在我的下一个电路板支持包版本中尝试一下,并告诉你它是否也能正常工作。 能否请您告诉我,在进行这些更改时,您使用的是哪个版本的 uboot 和内核? Re: How to keep logo from uboot to kernel on imx8mm. 我找到了一种方法,对我很有效。 我在内核中创建了一个预留内存节点,并在 fb-con 中显示了内容。在 u-boot 中,我用加载的帧缓冲区修复/填充预留内存节点。 这是为 imx8mn 设置的,但我也为 imx8mp 设置了类似功能 如果有人知道正确的方法或更好的方法,我很乐意倾听 Re: How to keep logo from uboot to kernel on imx8mm. 嗨,@topphysician、 我也没有找到解决办法。在我的测试中,我尝试了和你一样的操作,但最终还是出现了随机启动错误。 目前,我只能在uboot和内核启动之间短时间内显示屏关闭。 问候 Cedric Re: How to keep logo from uboot to kernel on imx8mm. 你找到解决办法了吗? 我什么办法都试过了,但都不太成功。我已经从 uboot 中删除了"mipi shutdown" (这样 uboot-splash 就会一直显示到内核),但当内核启动到一定程度时,屏幕开始逐渐消失。 Re: How to keep logo from uboot to kernel on imx8mm. 看起来与我的页面有些不同。 cpu.c 文件中没有使用 lcdif_power_down(),因为上述定义包含另一个条目: #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) lcdif_power_down(); #endif 我曾尝试在 mxs_video_remove () 函数中删除 device_remove () 和 mxs_remove_common () 调用,但这有时会在启动内核时陷入死锁。 此外,内核在启动的前两秒内直接禁用了我的显示器。因此,这次代码修改并没有真正的附加值。 您使用的是什么版本的 uboot 和内核? Re: How to keep logo from uboot to kernel on imx8mm. #if defined(CONFIG_VIDEO_MXS) - lcdif_power_down(); + /* lcdif_power_down(); */ #en 我只是注释掉了通话,关闭了液晶屏的电源。这样就不会出现无法预知的内核问题,也就不会在 U 盘启动后立即出现闪屏图像从中心位置随机移动的情况。 从日志时间来看,内核重新定位并开始执行代码需要 10 秒钟。 当内核初始化到达显示驱动程序时,任何闪屏偏移都会被驱动程序初始化纠正,然后写入内核相同的闪屏图像。 如果我让 uboot 给液晶屏掉电,我的黑屏时间会超过 10 秒。我将探索是否可以通过 lcdif_power_down()来取消内存映射,同时保持 LCD 背光打开等。 调试串行端口的内核日志。 [12:42:06.076]在 908056a0 处使用设备树,结束 90813a31 [12:42:06.083] [12:42:06.083]Starting kernel ... *** splash image sometimes shifts position *** [12:42:06.083] [12:42:17.085][0.000000] 在物理 CPU 上启动 Linux 0x0 Re: How to keep logo from uboot to kernel on imx8mm. 嗨,史蒂文、 你只在 uboot 中做了更改,显示屏在包括屏幕内容在内的整个内核启动过程中都能继续工作? 在我的尝试中,内核电源管理单元在内核启动过程中多次停止和重启 mipi 单元时遇到了很大的问题。 当我在 uboot 结束时禁用了 mipi 驱动程序关机后,我的内核在 3 次尝试中只有 2 次正确启动。因此,这在实践中是行不通的。 Re: How to keep logo from uboot to kernel on imx8mm. 我对 uboot 进行了代码修改,以保持显示驱动程序正常运行;但它偶尔会将闪屏随机向上或向右移动若干像素。 也许这就是他们关闭显示屏的原因...... Re: How to keep logo from uboot to kernel on imx8mm. 你好@Bio_TICFSL、 您添加的链接显示了如何将 Linux 企鹅更改为自己的徽标。但最初的问题是关于从 uboot 向内核传递闪屏的。 你今天也有解决方案吗? 此致 塞德里克 Re: How to keep logo from uboot to kernel on imx8mm. 你好@ruansy、 您已经找到解决这个问题的办法了吗? @Bio_TICFSL的链接很有趣,但只展示了如何用自己的徽标替换 Linux 企鹅。 我也在寻找关于如何在uboot中显示任何启动画面并保持活动状态直到Linux完成启动的解决方案。我用基于 imx6 的示例做了很多研究,但是 mipi 接口完全不同,启动 Linux 时的电源管理单元也完全不同。 因此,如果您有任何进一步的信息,我将非常感兴趣。 预先致谢 塞德里克 Re: How to keep logo from uboot to kernel on imx8mm. HI 如何在 uboot 中初始化 MIPI DSI 控制器并显示标识 Re: How to keep logo from uboot to kernel on imx8mm. 你好 ruansy、 也许这个链接能帮到您: https://developer.toradex.com/knowledge-base/splash-screen-linux 此致 Re: How to keep logo from uboot to kernel on imx8mm. 是的,我也想知道如何解决这个问题。从 u-启动 切换到内核显示屏时,屏幕始终是黑色的,并且无法连续显示徽标。如何解决这个问题? Re: How to keep logo from uboot to kernel on imx8mm. 电路板支持包 版本为 L5.4.70-2.3.0 Re: How to keep logo from uboot to kernel on imx8mm. 嗨,@topphysician、 我用 Linux 的 6.12.20 标签测试了你的补丁,用 imx8M Mini 测试了 U-启动。基本上,它对缩短U-启动和Linux之间的显示关闭时间有很大帮助。我本以为这次会彻底消除,但还是有一些,尽管比以前少了很多。 我对您的代码做了一些小改动,以便针对我的应用进行优化。 首先,我删除了 dtsi 文件中的 "splashFramebuffer "设置,现在可以动态计算这些值。这些硬编码值对我不起作用,因为我的 u-启动 支持 10 种不同图像大小的 Mipi 显示器。 最后,我的 "setFramebuffer "函数看起来是这样的: #include #include void setFramebuffer(void * blob) { int ret; int off; uint64_t fb_base; uint64_t fb_size; struct udevice *dev; struct video_priv *priv; if(uclass_get_device(UCLASS_VIDEO, 0, &dev) != 0) printf("ERROR: no video device available.\n"); priv = dev_get_uclass_priv(dev); if (priv) { printf("FB_BASE = %p Size=%d X=%d Y=%d stride=%d\n", priv->fb, priv->fb_size, priv->xsize, priv->ysize, priv->line_length); } // Read the fb base and size fb_base = (uint64_t)(priv->fb); fb_size = priv->fb_size; /* Find the splash_reserved node by compatible */ off = fdt_node_offset_by_compatible(blob, -1, "reserved,custom_splash"); if (off < 0) { printf("No splash_reserved node found\n"); return; } printf("Setting framebuffer at 0x%llx\n", fb_base); /* Write reg property: <0x0 base 0x0 size> as 4x u32 in big-endian */ uint32_t reg_prop[4]; reg_prop[0] = cpu_to_fdt32((uint32_t)(fb_base >> 32)); reg_prop[1] = cpu_to_fdt32((uint32_t)(fb_base & 0xFFFFFFFF)); reg_prop[2] = cpu_to_fdt32((uint32_t)(fb_size >> 32)); reg_prop[3] = cpu_to_fdt32((uint32_t)(fb_size & 0xFFFFFFFF)); ret = fdt_setprop(blob, off, "reg", reg_prop, sizeof(reg_prop)); if (ret < 0) { printf("Failed to set reg property: %d\n", ret); return; } /* Optional: also set 'splash-size' property as 64-bit big-endian */ ret = fdt_setprop_u64(blob, off, "splash-size", fb_size); if (ret < 0) { printf("Failed to set splash-size property: %d\n", ret); return; } /* Set status property to "okay" */ ret = fdt_setprop_string(blob, off, "status", "okay"); if (ret < 0) { printf("Failed to set status property: %d\n", ret); return; } /* Optional: update node name to reflect new address, e.g. splash@44000000 → splash@fb_base */ char node_name[64]; snprintf(node_name, sizeof(node_name), "splash@%llx", fb_base); ret = fdt_set_name(blob, off, node_name); if (ret < 0) { printf("Failed to rename node: %d\n", ret); return; } printf("Framebuffer reserved memory updated in DTB.\n"); }
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开发MPC5554的工程 请问我要开发MPC5554的工程,需要怎么安装开发环境,怎么搭建简单工程,是安装CodeWarrior for eTPU v10.3 Windows.exe吗 安装步骤有配套的中文说明吗 回复: 开发MPC5554的工程 应该是支持的 回复: 开发MPC5554的工程 用于 MPC5554 的 Code Warrior V2.10 支持 C99 标准吗? Re: 开发MPC5554的工程 好的,非常感谢您! Re: 开发MPC5554的工程 我确信 CW 2.10 支持 MPC5554: lukaszadrapa_0-1708583306177.png Re: 开发MPC5554的工程 回答一些简单的问题应该不成问题。但如果是更耗时的东西,我就不能保证了...... 另请注意,该产品的产品寿命已于 2019 年到期: https://www.nxp.com/products/nxp-product-information/nxp-product-programs/product-longevity:PRDCT_LONGEVITY_HM 现在,供应情况取决于客户的需求。如果未来几年宣布 "生命终结",请不要感到惊讶。 如果你的产品寿命应该更长,我会重新考虑使用这个设备。 Re: 开发MPC5554的工程 网页显示里面有这些型号没有5554 这个会影响使用嘛 MPC55xx device support: MPC5514E/G MPC5515S MPC5516E/G/S MPC5517E/G/S MPC5533 Re: 开发MPC5554的工程 好的谢谢您 这个是别人指定用的型号我们也没有办法 如果最后还是用这个MPC5554开发项目遇到问题可以请教您们嘛 Re: 开发MPC5554的工程 你好@smallyang CodeWarrior Classic 2.10 支持 MPC5554: https://www.nxp.com/design/design-center/software/development-software/codewarrior-development-tools/codewarrior-legacy/codewarrior-development-studio-for-mpc55xx-mpc56xx-classic-ide-v2-10:CW-MPC55XX_56XX 快速入门指南可在 "文档 "部分找到。 用于 eTPU 的 CodeWarrior 则不同--它可以用于修改 eTPU 库,而实际情况可能并非如此。 无论如何,请注意,不建议将 MPC5554 用于新设计,因此我们不支持客户使用此设备启动新项目。 此致, Lukas
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iMX8QM 和 LPDDR4 内存错误 您好, 我们为您介绍南亚 NT6AN512T32AV-J1I(https://www.nanya.com/en/Product/4404/NT6AN512T32AV-J1I)我们的 Apalis iMX8 (i.MX8QM) 模块上的内存可替代 Micron MT53D512M32D2DS-046 IT:D (MT53D512M32D2DS-046-AIT-D ) 我们查看了时序规格,Nanya 部件似乎可以直接替换 Micron 部件,因为两者的时序要求似乎相同。 我们使用与美光版本(Linux 电路板支持包 + Memtester [mem tester-4.6.0.tar.gz] 相同的测试设置)测试了几个配备 Nanya 内存的模块。当然,我们还在美光模块上重新运行了测试。 Nanya 内存在不同的温度范围内表现良好,但在较高的温度范围内(约 50°C 至约 80°C),我们在 Memtester 的 Bit Spread(但不是唯一的)测试中观察到以下故障(这些故障是我们遇到的故障总数的一部分): 失败:偏移量 0x00000000031a9a80 中的 0xffffffffffffffffffff != 0xfffffffffffbffffffffff. 失败:偏移量 0x0000000009eb5440 中的 0xffffffffffffffffffff != 0xfffffffffffbffffffffff. 故障:偏移量 0x000000000172b040 中的 0xffffffffffffffffffff != 0xfffffffffffbffffffff。 故障:偏移量 0x000000000792e570 中的 0xfffffffffbffffffff != 0xffffffffffffffffffffff。 FAILURE: 0xffffffffffffffff != 0xfffffffffbffffff at offset 0x000000000a13fb00. 值得注意的是,只有当我们在 -40°C 开始测试,并在不重启的情况下升至 85°C 时,才会出现这些错误。如果我们从 85°C 开始测试,然后降温至 -40°C,则不会出现任何误差。因此,我们怀疑 LPDDR4 在零下 40 度进行训练会影响内存的可靠性(在零下 40 度进行训练时可能会出现信号完整性问题)。 我们还转储了一些与内存训练有关的 DDR 控制器寄存器,我们注意到两种内存类型之间存在显著差异(见附件)。我们怀疑可能需要为南亚内存调整某些终止或驱动强度参数,但不确定是哪些参数。 我们还附上了 RPA(寄存器编程辅助工具)Excel 表,其中包含目前用于两种内存类型的 DDR 控制器配置。 欢迎提出任何意见或建议,但具体来说,我们有以下问题: 对训练结果寄存器进行比较是否有助于找出根本原因或突出两种存储器类型之间的关键差异? 你对内存配置有什么建议以改善训练和信号完整性吗? 提前感谢您的支持。 i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus Re: iMX8QM and LPDDR4 memory errors 你好@hongting_dong、 我可以在两种不同的外部温度下进行采集:-20(固定温度下 2 小时后)和 +25(开启 30 分钟后)。 DDR0 字节 2 很奇怪,请告诉我你的看法。 此致敬礼, 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 创建基线并熟悉写入眼生成程序后,我们建议采取以下步骤进行温度测试: 将所需的 LP4 设备降至 -40C(在我们的实验室中,我们使用热流) 达到-40摄氏度后,启动板并启动VTSA工具(此时,想法是将DDR在-40摄氏度下初始化/训练) 在每个字节通道上执行 Write Eye 测试 完成后,将温度提高到 25C,无需通电、循环/重新启动板或工具,即可将经过训练的值保持在 -40C 在 25C 温度下,对每个旁路重新进行 "写眼 "操作 完成后,将温度提高到85摄氏度,无需重新启动板或工具,即可将经过训练的值保持在-40摄氏度 在 85C 温度下,对每个旁路重新进行 "写眼 "操作 谢谢! 顺祝商祺! Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 请使用以下链接进行测试 https://community.nxp.com/t5/iMX-and-Vybrid-Support/i-MX8QM-i-MX8QXP-i-MX8DXL-DRAM-Virtual-Timing-and-Signal/ta-p/1321350 顺祝商祺! Re: iMX8QM and LPDDR4 memory errors 你好, ,请提供 iMX8QM 的 VTSA。 据我所知,这种 SoC 没有这样的工具。 谢谢, 。 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 想加倍了解一些细节。 1. 你能用更高的电压测试启动吗? 2. 您能否获得 VTSA 结果,以了解 NANYA 余量在低温或跨温条件下是否不佳? 3. 在历史记录中,更改 ODT / 硬盘强度没有任何帮助,对吗? 4. 如果将 CA Vref 设置为 0,有什么帮助吗? 谢谢! 顺祝商祺! Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 是的,你说得对。 Re: iMX8QM and LPDDR4 memory errors "DQS 间隔振荡器" 数据表章节的补充说明也在 JEDEC 第 209-4 号标准:"低功耗双倍数据速率 4 (LPDDR4)" 中进行了报告。 BR, Emanuele Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 内存数据表报告: DQS 间隔振荡器随 着同步动态随机存取存储器(SDRAM)芯片上电压和温度的变化,DQS 时钟树延迟将发生变化,可能需要重新训练。 这表明,DQS2DQ 培训应得到支持,而且在某些情况下可能是必要的。 恩智浦是否考虑过禁用 DQS2DQ 可能会导致某些依赖该训练的内存芯片出现故障? 恩智浦能否帮助我们确定一种变通办法或解决方案,并评估当前的勘误是否可以解决? 我们观察到以下行为: 如果我们从 85 °C 开始测试,然后让温度降至 -40 °C,则不会出现任何问题。 相反,如果我们从较低的温度(如-10 °C)开始升温(如升至 60 °C),即使在这个较低的温度范围内,我们也能观察到内存故障。 我们还注意到,定期暂停到 RAM 并恢复可以解决这个问题,这可能是因为,正如您所提到的,DQS2DQ 训练是在恢复过程中执行的。 我们启用了 DQS2DQ 训练,但遗憾的是,结果仍然是负的(甚至更糟)。 这些信息对您的分析有用吗? 致以最诚挚的问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@pengyong_zhang、 我测试了所有介于 0x40 和 0x47 之间的 MR12 值。 亲切的问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 很抱歉,除了在运行过程中 禁用DQS2DQ 训练 外,别无他法。 顺便问一下:您的测试结果如何,我之前告诉过您通过更改 MR12 的值来更改 CA Vref,并且除了 MR12 之外不要更改任何参数? BR. B.R Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 除了完全禁用之外,还有其他选择吗? 亲切的问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 我们的在勘误表中,ERR050102:动态随机存取存储器(DRAM):不支持定期进行基于硬件的 DQS2DQ 校准。 说明 如果启用基于硬件的 DQS2DQ 周期性校准,由此产生的延迟可能会导致某些关键子系统(如显示和成像接口)出现运行不足、 或最坏情况下出现锁定,从而影响其 性能。 解决方法 当前,DQS2DQ 校准仅在开机时以及从低功耗电源模式恢复时进行。迄今为止,在整个工艺、电压和温度范围内均未发现故障或 稳定性问题。 B.R Re: iMX8QM and LPDDR4 memory errors 你好@pengyong_zhang、 是的 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 Nanya 的意思是这个错误是由于板在操作期间没有定期进行 DQS2DQ 培训造成的? B.R Re: iMX8QM and LPDDR4 memory errors 你好,@张鹏勇,@董虹婷、 南亚公司对这些行为进行了分析,得出了以下结论: 根据 LA MRS 设置确认,MR18/MR19 在记忆测试期间被禁用。 NTC 建议在平台上启用 MR18/MR19,因为如果平台不执行 Tdqs2dq 偏移,则默认设置可能无法满足 NTC 设备的要求。 我在 RPA、SCFW 或 i.MX8QM 参考手册中找不到任何与 MR18/MR19 寄存器相关的设置或信息。 由于这些是 RAM 侧的只读寄存器,我的理解是内存控制器或 SCFW 应在运行时读取并使用它们。 您能帮我确定我们该如何继续吗? 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 保持ZPROG_ASYM_PD_DRV_DQ_48 和 ZPROG_ASYM_PD_DRV_DQ_60 为默认值。请勿更改。 然后逐步测试不同的 MR12 值。抱歉,我无法重现你的问题,因为我没有你的测试板和环境。因此,您需要自己进行测试,找到合适的 Vref 值。此外,我认为最好的办法还是请 Nanya 谈论这个问题,看看他们能否重现您的问题并给出解决方法。 B.R Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 我测试了 MR12,只是将 0x47 更改为 0x40。 以及 ZPROG_ASYM_PD_DRV_DQ_48 和 ZPROG_ASYM_PD_DRV_DQ_60。 每次配置都失败。 我真的不知道这些测试是好是坏。 亲切的问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 您运行了关于 MR12 寄存器更改的测试吗?测试结果如何?运行此测试时,除了 MR12 之外,不要更改任何参数。 B.R Re: iMX8QM and LPDDR4 memory errors 你好,@张鹏勇,@董虹婷、 你能否特别关注这一事实: > 值得注意的是,只有当我们在 -40°C 开始测试,并在不重启的情况下升至 85°C 时,才会出现这些错误。 作为一种变通方法,我们能否通过修补 scfw,在工作系统上重新触发内存训练? 鉴于我们报告的错误类型(比特翻转),是否有经过培训的"参数" 可以帮助我们找出根本问题? 预先致谢, 。 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 测试了您的建议,还测试了 40 -> 60。 两项测试均在7个板上均失败,没有任何重大变化(改善或恶化)。 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 是的,我是说 24.8,24.4、24 等等。 B.R Re: iMX8QM and LPDDR4 memory errors 您好, ,内存上有记录: Nanya2447 NT6AN512T32AV-J1I 9423W1EF 3 TW 如果这是您需要的信息,请告诉我。 谢谢! 问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@pengyong_zhang、 你建议修改 MR12,我是否也要修改 MR14? 对不起,我还有一个疑问。当您说"测试从 25.2% 向下" 时,您指的是 24.8 还是 24.4、24,以此类推,还是反过来(25.6,26,26.6,以此类推)? 谢谢, 。 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 还请更新信息: Nanya 故障设备信息: MFD 日期代码: 批号是 : 我记得你试过 Nanya 的最新设备部分了吗,他们的设备部件在 ZQ cal 中有一些更新 顺祝商祺! Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 事实上,我不确定哪个 DS 值或 ODT 值能解决这个问题。 不过,您还可以尝试另一种方法: 通过 SCFW imx8qm_dcd_1.6GHz.cfg 文件修改 MR12 值,请参考以下代码。 DATA 4 DDR_PHY_MR12_0 0x48   将测试从 25.2% 调低。 依次测试。   pengyong_zhang_1-1750667443314.png B.R Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 谢谢你的提示。 我们已经进行了测试,将 RPA 中的 ZPROG_DRAM_ODT 和 ZPROG_ASYM_PD_DRV 从 40 设置为 48-寄存器 DDR_PHY_ZQ1PR0(DQ 总线阻抗控制)(也从 40 设置为 34),没有任何区别。 请告诉我您对只测试 ZPROG_ASYM_PD_DRV 至 48(或更高值)的意见。 此致, 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 收到您的信息,您可以使用我们的 MX8QM_B0_LPDDR4_RPA_1.6GHz_v23.xlsx 文件,选择不同的 DS 值,然后重新运行测试,看看能否解决此错误。因为您的错误是在环境温度从低到高时发生的。我建议你可以试试 40->48 的 DS。并查看测试结果。 pengyong_zhang_0-1750397500154.png B.R Re: iMX8QM and LPDDR4 memory errors 你好, 已经完成。他们希望存储器能在这种条件下工作。 我想知道我们是否可以调整配置来修复这些错误:终止、驱动强度、延迟以及一般的定时。 问候, Emanuele Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 那么,我认为您应该请 Nanya 的供应商谈谈这个错误。询问他们的 DDR 能否在测试场景下通过该测试。 这与复员方案培训无关。 B.R Re: iMX8QM and LPDDR4 memory errors @pengyong_zhang 你好、 是的,我们做到了。它可以正常工作,不会出现任何错误。 埃马努埃莱 Re: iMX8QM and LPDDR4 memory errors 你好@emanuele79 你有没有试过使用美光 动态随机存取存储器(DRAM) 运行同样的测试看看是否也会出现这个错误日志? B.R
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S32K3: AC_load_on_Job_Startについて 1.リファレンスマニュアルによると、RWW の問題を回避するには、AC_load_on_Job_Start を有効にする必要があります。 しかし、下図のように有効にすると、Fls_ACWriteSize と Fls_ACWriteRomStart はまだ未定義です (Fls_ACEraseSize と Fls_ACEraseRomStart と同じ)。 Jojo_Hu_0-1750821620784.jpeg Jojo_Hu_1-1750821642119.jpeg Jojo_Hu_3-1750821740692.png SO、この問題をどうやって解決したらいいでしょうか? 2. AC_load_on_Job_Start が無効で、書き込みと消去の両方が非同期モードの場合、データ フラッシュの書き込み/消去中にコード フラッシュ ブロックの書き込み/消去をCANますか? 皆様のサポートをお待ちしております、ありがとうございます! Re: S32K3: about AC_load_on_Job_Start こんにちは、 アプリケーションとブートローダのメモリ配分は次のとおりです。 ブートローダで実行中にアプリケーションを消去して書き込みたい場合、起動時の AC ロードが有効になっていると、PreTaskHook の 2 番目の図に示すようにオンコア MPU を構成する必要がありますか? Jojo_Hu_0-1757918173892.png Jojo_Hu_1-1757918311233.png Re: S32K3: about AC_load_on_Job_Start はい、C40_Ip_AccessCode は RAM にコピーされます。 Re: S32K3: about AC_load_on_Job_Start ROM 内のコードのどの部分が RAM 内のこのアドレスに配置されますか? この機能? Jojo_Hu_0-1751978216903.png Re: S32K3: about AC_load_on_Job_Start 私のテスト コードでは、コンフィギュレータでこれらのアドレスを初期化しました。SO、未使用の RAM を指すようになりました。 lukaszadrapa_0-1751955715691.png Re: S32K3: about AC_load_on_Job_Start これらの変数をどのように定義すればよいでしょうか? Jojo_Hu_0-1751540048260.png Re: S32K3: about AC_load_on_Job_Start このバージョンで簡単なテストをしました。消去されるはずのセクターが Fls コードと同じフラッシュ ブロック内にある場合、コードが期待どおりに RAM にコピーされ、セクターが正常に消去されていることがCANます。あなたの側で何が起こっているのか分かりません... Re: S32K3: about AC_load_on_Job_Start @lukaszadrapa 質問1については、 皆様のサポートをお待ちしております。ありがとう。 Re: S32K3: about AC_load_on_Job_Start こんにちは、 1の場合: SW32K3_S32M27x_RTD_4.4_4.0.0_P20_D2403 Re: S32K3: about AC_load_on_Job_Start こんにちは@Jojo_Hu 1. それはどの RTD バージョンですか? 2. フラッシュ ブロック間では Read-While-Write がサポートされます。たとえば、データ フラッシュがプログラムまたは消去されている間に、コード フラッシュからコードを実行CAN。一度に実行できるプログラムまたは消去操作は 1 つだけであることに注意してください。 よろしくお願いいたします。 ルーカス
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S32K3: about AC_load_on_Job_Start 1. According to the referrence manual, we need to enable AC_load_on_Job_Start to avoid RWW problems. But when I enabled it as below picture, Fls_ACWriteSize and Fls_ACWriteRomStart are still undefined (the same as Fls_ACEraseSize and Fls_ACEraseRomStart). Jojo_Hu_0-1750821620784.jpeg Jojo_Hu_1-1750821642119.jpeg Jojo_Hu_3-1750821740692.png so how to solve this problem please ? 2. If AC_load_on_Job_Start is disabled and both Write and Erase are in Async mode, can the code flash block be writing/erasing while data flash be writing/erasing ? Looking forward to your support, thank you! Re: S32K3: about AC_load_on_Job_Start hi, The memory distribution of Application and Bootloader are as follows. If we want to erase and write Application while running in bootloader, and Ac load at startup has been enabled, do we need to configure the on-core MPU as mentioned in the second picture in PreTaskHook ? Jojo_Hu_0-1757918173892.png Jojo_Hu_1-1757918311233.png Re: S32K3: about AC_load_on_Job_Start Yes, C40_Ip_AccessCode is copied to RAM.  Re: S32K3: about AC_load_on_Job_Start Which parts of the code in ROM will be placed at this address in RAM ?  This function ? Jojo_Hu_0-1751978216903.png Re: S32K3: about AC_load_on_Job_Start In my test code, I just initialized these addresses in configurator, so it points to unused RAM: lukaszadrapa_0-1751955715691.png Re: S32K3: about AC_load_on_Job_Start how should I define these variables? Jojo_Hu_0-1751540048260.png Re: S32K3: about AC_load_on_Job_Start I did quick test in this version. If the sector which is supposed to be erased is in the same flash block as Fls code, I can see that the code is copied to RAM as expected and the sector is successfully erased. Not sure what's going on on your side... Re: S32K3: about AC_load_on_Job_Start @lukaszadrapa  for question 1, looking forward for your kind support. Tks. Re: S32K3: about AC_load_on_Job_Start hello, for 1:  SW32K3_S32M27x_RTD_4.4_4.0.0_P20_D2403 Re: S32K3: about AC_load_on_Job_Start Hi @Jojo_Hu  1. Which RTD version is that? 2. Read-While-Write is supported between flash blocks. For example, the code can run from code flash while data flash is being programmed or erased. Notice that only one program or erase operation can run at a time.  Regards, Lukas
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Two ColdFire Families Announced Today In case you missed it... today Freescale announced two new ColdFire families. These two families, the MCF5222x and MCF5223x (that's right, five digit part numbers) are closely related to the MCF5211/2/3. The MCF5223x (x=0-5) family of devices are single-chip solutions with an integrated Ethernet interface (FEC) and an on-chip Ethernet Physical Layer (PHY). Here is a link to the superset device: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF52235&nodeId=0162468rH3YTLC00M98090 The MCF5222x (x=1,3) family of devices are single-chip devices that feature an integrated USB host and On-The-Go (OTG) controller. Here is a link to the superset device: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF52223&nodeId=0162468rH3YTLC00M98145 Message Edited by mnorman on 04-04-2006 12:22 PM General Re: Two ColdFire Families Announced Today Regretfully, the seminars are currently limited to the Americas. It appears that there will probably be one in September or so in Zurich, Japan, where I currently reside. So, as soon as a DEMO board becomes available, I'll try to get one. Since the DEMO board has a larger user base than the EVB (at least for the DEMO board, I have a lot of contacts with one, but almost none with the EVB), we prefer to support it. In fact, we have half a dozen different projects that were prototyped using the DEMO board because of its adorable housing and power supply, which allow customers to use it until their board arrives Here. Re: Two ColdFire Families Announced Today Hi Marc, The M52233DEMO board is being held up by ROHS compliance. However, you can talk to your distributor to order the M52230DEMO board, which is not ROHS compliant. Ed Re: Two ColdFire Families Announced Today So when will the M52233DEMO become available other than on seminars? I noticed that the manuals can be found on the AXMAN Manufacturing web site but those people don't seem to sell the board either... ...and I want it! Re: Two ColdFire Families Announced Today Thanks Mark. Great answer! Re: Two ColdFire Families Announced Today Hi Tom   uTasker requires about 54 bytes of memory for each tcp socket and about 40 bytes for a http session. (A http session needs one TCP socket and the number of http sessions is defined by #define NO_OF_HTTP_SESSIONS). This means, for example,  that 4 parallel http sessions will require about 376 bytes of SRAM. I say 'about' because there are a number of TCP settings which can influence it slightly (eg, if you want to support MSS, windowing, etc.).   However the web server is a bit of a special case since it is possible to reconstruct messages when repetitions are needed to be performed (it is not necessary to backup transmitted data since it can be reconstructed when needed, even when dynamically generated. The source is essentially in a file system and can be fetch as required.).   Other TCP protocols can have very different characteristics - a good example is an application where data received from a serial port is being sent over a TCP connection. In this case the data has to be buffered locally and deleted only when you know that the data has been successfully delivered. If a repetition is necessary it must still be available otherwise no repetition will be possible. A second fairly similar case is when debug messages from code are being  formated to a TCP connection (the connection used as a sort of debug output as is often done over the serial port). In this case the transmit data is being put quite randomly into the output buffer and must also be stored until completely delivered as the code is non capable of reconstructing such messages if they need to be repeated.   For this second case the uTasker allows TCP sockets to be individually set up with a transmit buffer, each socket's buffer is user definable depending on the application's requirements. The TCP code then takes over the work of managing the buffer transparently. Of course this buffer eats memory... for Telnet debugging I find a buffer for this socket of about 2,5k a good compromise between performance and comfort (of course each used socket will need its own buffer...). When a buffer becomes full (queued TCP frames have not yet been delivered) it causes flow control to kick in which is noticable in reduced throughput - hopefully for only a short time, but noticable nevertheless [eg. the serial port case would have to deassert CTS or send XOFF until more place is available.]   Therefore the answer to the memory utilisation is not so easily answered in a general case, it will always depend on the application's individual requirements and protocol used, but it is best when it can at least be easily configured and controlled. Browse to a uTasker demo on-line at http://212.254.22.36 and look at the administrator web side. It will show you the worst case memory utilisation of stack and heap it has experienced. If you telnet to it "telnet 212.254.22.36" or ftp it, you can see that the heap size will change (grow slightly) (command a reset of the device from the administrator side so that it starts off fresh beforehand - It takes memory only when actually required so the value will grow to a max. after which you can be sure that it will never require more). By the way the uTasker supports also dynamic heap size allocation so the heap available can be easily optimised to real requirements, even automatically for multiple configurations.   On top of the discussed memory use, which is dynamic, there is also some basic code RAM requirements - static. tcp and http, for example, require 3 resp. 60 additional bytes of static ram, irrespective of the number of sessions to be used. There is a comparison of static FLASH and RAM sizes in the uTasker tutorial - see page 16 of the following document. (the compiler used is also quite critical...!!) http://www.mjbc.ch/documents/uTasker/NE64/uTaskerV1.2-Tutorial.PDF The FLASH requirements on the Coldfire increase by about 80% (unfortunately) due to the fact that it is a 32 bit machine and has longer instructions but the Coldfire demo application is still only about 50k in size, showing that quite a lot can be packet in to the M5223X...(It takes up about 24k on a 16 bit device or an ARM in Thumb mode)   Regards   Mark www.mjbc.ch   Re: Two ColdFire Families Announced Today Hello, Mark, can you tell me how much of the 32k ram is used by utasker and the tcp/ip stack for the following two conditions: 1. No active tcp connections 2. One active tcp connection. If the buffer size is configurable, what is the min/max? Does anyone know what these numbers are for the Interniche rtos/stack? The reason I am asking: Lets say I am running an application that uses the rtos and tcp/ip stack to create a web server. When a client connects with a web browser a tcp connection is established that will require a certain amount of ram to maintain (until it is closed by the web server). I need to make sure my application does not use too much much ram, so the tcp stack has enough space when it needs it. The next logical step is to support 2 simultaneous TCP connections. One connection to do the actual product function (for example, data logging), and the second for the web server to handle configuration of the device. There will be times when the device is functioning and a user is accessing the web server at the same time. This would require enough resources for 2 TCP connections at the same time. Thanks, Tom Re: Two ColdFire Families Announced Today Hi Jakob No I didn't try the Interniche stack but I managed to port our uTasker to the new device. See the following with on-line demo: http://forums.freescale.com/freescale/board/message?board.id=CFCOMM&message.id=274 If you would like to see it running on your demo board you can load the demo project from here (it has a web server, ftp, telnet and smtp). http://www.mjbc.ch/software/uTasker/M5223X/uTaskerV1.2beta005_m5223X.s19 For educational and hobby use it if free of charge, including free email support, coming with an operating system, TCP/IP stack and M5223X simulator - the complete project runs in real time on a PC and can be tested in a real-network where it is not noticable that it is a simulator and not the real device running. It can save a lot of project development time since complete applications can be coded and tested before having to move to the real target - also the internal coldfire peripherals are simulated so low level debugging is very comfortable. Cheers Mark Butcher www.mjbc.ch Re: Two ColdFire Families Announced Today Hi Mark, did you try the tcp/ip stack from interniche? http://www.freescale.com/files/32bit/doc/support_info/ColdFire_Lite_Doc.zip i am working on my diploma with the demoboard . best regards jakob Re: Two ColdFire Families Announced Today Hi Moderator   Perhaps you can give me some tips with the problem which I now have: I received the M52235EVB. It is supplied with a CD with the GNU compiler for the Coldfire. I would like to make a GNU project (as well as CodeWarrior). I think that the the CD is the wrong one since it has only manuels and tools for older Coldfire version but I think that I have been able to download everything from teh Freescale web site. Also teh install of the GNU compiler from the CD didn't work - it hung every time at the end the the compiler didn't work due to a missing DLL (at least that is what the error message said). I downloaded a GNU 4.1.0 binary for the Coldfire which is the latest version.   1. I can compile my source code but I can't work out how to control it when linking. With the HCS12 I used a file called memory.x to control this but it seems as though this is not used with the Coldfire.   2. The linker always complains that it can't find the entry symbol _start. My HCS12 project has this defined in the vector table but I assume it is missing from some start up code since I also have a similar vector table - although I don't yet know whether it is used in the same manor (?).   3. I have read in the GCC docs that one should define mcpu=5200 for the coldfire but this just results in an error. I have found that mcpu=5208 works but don't know whether this is correct for this Coldfire type.   4. I don't seem to be able to find any documentation about linking for the Coldfire. Is there any example project somewhere which could help?   Many thanks in advance.   Regards   Mark Butcher www.mjbc.ch Re: Two ColdFire Families Announced Today Hi Moderator Unfortunately the seminars are presently only available in the Americas. I have seem that there is likely to be one in Zurich, Switzerland, where I am, in September or so. Therefore I will see whether I can grab a DEMO board as soon as it is available. We prefer to support the DEMO boards since the user base is must greater than the EVB (at least this is the case for the DEMO9S12NE64 - I have many contacts with one but almost none with the EVB - we have even half a dozen different projects which were prototyped with the DEMO board since its cute housing and power supply make it suitable to even give to customers until their board arrive....) Regards Mark Butcher www.mjbc.ch Re: Two ColdFire Families Announced Today Marc, The EVB and DEMO boards both will come with "ColdFire TCP/IP Lite" by InterNiche. See link below for more information on this stack: http://www.freescale.com/files/32bit/software/protocol_stacks/COLDFIRE%20TCPIP%20LITE.zip Re: Two ColdFire Families Announced Today Hey Mark, The M52235EVB is available to the public today, the low-cost M52233DEMO board will be be available to the public soon, but can be acquired faster through some upcoming seminars. Read below: COMING SOON: The M52233DEMO, an ultra-low cost version of the M52235EVB. Sign up for the Freescale ColdFire Ethernet Seminar Series and be one of the first to use this low cost, fully functional development tool. This board will be available to the public in late May or early June. To sign up for the seminar, follow the link: http://www.freescale.com/files/abstract/overview/TSP_8870_COLDFIRE_LP.htm?tid=tcRDck Re: Two ColdFire Families Announced Today What kind of TCP/IP software comes with these demo boards? Re: Two ColdFire Families Announced Today Hi I would like to order the new DEMO board but didn't find a link to it. Is it already deliverable and if so, how best to order? We have been supporting the NE64 with the uTasker operating system and integrated TCP/IP stack for a year or so and it seems logical to upgrade support to the new Coldfire devices with Ethernet. The uTasker V1.2 for the NE64 is presently being released, including free serial debugger and software to convert the DEMO9S12NE64 into LAN capable BDM. There are online demos - see http://212.254.22.36:8080 for web cam; http://212.254.22.36 and http://212.254.22.36:8081 for on line devices (login with ADMIN / AL6000S and anon / anon resp.). A simple web based NE64 BDM is online at http://212.254.22.36:8083 also using anon / anon login. The uTasker environment includes a unique chip simulator allowing almost complete real-time development and debugging on PC. It is free for educational and non-commercial use, with free email support - anyone interested can contact me for application. There is a new complete project with tutorial for the NE64 (which is planned to be upgraded to Coldfire support) demonstrating powerful FTP and HTTP features. If someone at Freescale contacts me directly with an Email address I will send over a copy under the educational license for evaluation - you may be suprised at what it can do...! [needs VisualStudio 6.0 or higher for the simulation environment and compiles also to target]. Cheers Mark Butcher ww.mjbc.ch Re: Two ColdFire Families Announced Today airswit wrote: is there a chance that any of those will be drop in compatible with the 5213? I am in the process of designing a single board computer around this controller, but wouldn't mind a USB or ETHERNET connection as well. Also, is there any word on when these will be available for sample/purchase? More or less. The USB OTG versions (MCF52221 and MCF52223) drop into the 64-pin LQFP/QFN 5211/2/3 footprint with the proviso that the 16-bit timer pins GPT[3:0] are replaced by USB_DPLS, USB_DMNS, USB_VDD, and USB_VSS. The same applies to the 81-ball MAPBGA versions of these same families, except that the missing GPT pins now replace the dedicated PWM pins. The PWMs are available as second functions of the GPTs, just as they are on the 5211/2/3. The 100-pin LQFP is a little trickier, as the PWM and GPT pins are interleaved on the MCF5211/2/3. The GPT pins still replace the PWM pins (as is the case on the 81-ball MAPBGA), but they've been shifted up and down to wedge the 4 dedicated USB pins between them. One last tidbit: The MCF52221/3 take a 48 MHz crystal to supply both the reference for the system PLL and the USB. This is a change from the MCF5211/2/3. BTW, the Ethernet parts (MCF5223x) are designed to drop into the 80- and 112-pin 9S12NE64 footprints, but the differences are a little more extensive (S12 BDM vs. ColdFire BDM, no flow control on S12 SCI vs. flow control on ColdFire UARTs, etc). Message Edited by jwbodnar on 04-06-200602:37 PM Re: Two ColdFire Families Announced Today See the press release below for more information on sample availability: http://biz.yahoo.com/bw/060404/20060404005598.html?.v=1 Pricing and Availability The MCF5223x is now available in sample quantities, with production quantities planned for late 2006. MCF5222x samples are planned for June 2006, with production quantities planned for late 2006. Suggested resale pricing in 10,000-piece quantities start at $5.49 (USD) for the MCF5222X devices and at $7.99 (USD) for the MCF5223X devices. The M52233DEMO demonstration board is available now for the suggested resale price of $99 (USD). The M52235EVB evaluation board is available for the suggested resale price of $299 (USD). MCF5213 vs MCF522xx pin compatibility I know for a fact that the Ethernet device M5223x is not pin to pin compatible with the M5213 rather it is pin compatible with the MC9S12NE64. On the other hand, the USB device M5222x is pin similar to the MCF5213. The main difference are the pins driving USB signals. See pg. 15 in the data sheet: http://www.freescale.com/files/32bit/doc/data_sheet/MCF52223DS.pdf Re: Two ColdFire Families Announced Today is there a chance that any of those will be drop in compatible with the 5213? I am in the process of designing a single board computer around this controller, but wouldn't mind a USB or ETHERNET connection as well. Also, is there any word on when these will be available for sample/purchase?
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带 HSM 的 CST3.4.0 您好, 我正在使用最新的 CST-3.4.0& ,我想使用第三方 HSM 探索 CST-3.4.0。我按如下方式配置了 openssl.cnf、 openssl_conf = openssl_init [openssl_init] engines = engine_section [engine_section] pkcs11 = pkcs11_section [pkcs11_section] #从 OpenSC 编译的 OpenSSL PKCS11 的路径 - libp11 dynamic_path = /usr/lib/x86_64-linux-gnu/engines-1.1/libpkcs11.so MODULE_PATH = /home/jbhaijy/digicert/smtools-linux-x64/smpkcs11.so 我使用 -b pkcs11 选项运行 CST,通过 HSM 对图像进行签名,但却出现了以下错误。 ./cst --verbose -b pkcs11 -i dev_spl.csf -o dev_spl.bin 安装 SRK 安装 CSFK 未找到证书。 文件 pkcs11 中的公钥证书无效:model=DigiCert%20PKCS%2311;manufacturer=DigiCert;serial=SS0123456789;token=Virtual%20PKCS%2311%20Token;id=%36%34%33%39%61%63%61%32%2D%35%36%61%30%2D%34%64%64%63%2D%39%36%30%39%2D%65%62%64%39%31%63%36%33%65%33%62%39;object=imx6-hab-csf2-key-test;type=private 请帮我找出问题所在。 感谢您的支持。 Re: CST3.4.0 with HSM 我正试图使用带有 AHAB 的 imx93 Digicert 完成签名。 我能够同时签署 os_cntr_signed.bin 和 imx-boot-imx93-var-som-aski-sd.bin-flash_singleboot_gdet 但是一旦我尝试使用 ~/cst-4.0.0/linux64/bin/ahab_image_verifier 对其进行验证后 我得到的结果就不连贯了: 通过执行: ahab_image_verifier os_cntr_signed.bin 0 0 0,我得到了 签名块: 版本: 0 长度: 2648 字节 标签: 0x90 证书偏移量:0x0 SRK 表/数组偏移量:0x 10 SRK 表:标签:0xD7 长度:2 112 字节版本:66 SRK 记录: 标签:0xE1 长度:527 字节 签名算法: RSA 哈希算法:S HA2_384 密钥大小/曲线: RSA4096 SRK 标志:C A 标志 模数 (N):... 签名验证失败 在做的时候:ahab_image_verifier imx-启动-imx93-var-som-aski-sd.bin-flash_singleboot_gdet0 0 我得到了 签名块: 版本:0 长度:400 字节 标签:0x90 证书偏移量:0x0 SRK 表/数组偏移量:0x10 SRK 表:标签:0xD7 长度:308 字节 版本:66 SRK 记录: 标签:0xE1 长度:76 字节签名算法:ECDSA 哈希算法:SHA2 _256 密钥大小/曲线:PRIME256V1 SRK 标志:无 X 坐 标:... Y 坐标:... ...... 签名验证成功 我使用了相同的 csf.cfg 作为 cst-signer 的输入,因此 cst 的 .csf 中使用了相同的 SRK 表和数字证书令牌。文件 有人有线索吗?我也在这里提出了这个问题 Re: CST3.4.0 with HSM 您可以从https://www.nxp.com/search?keyword=IMX_CST_TOOL下载 默认情况下,该 CST 工具支持 HSM,但您需要配置 CSF,以便从 HSM 获取已签名的图像。 请查看该工具的文档,了解更多详情。 Re: CST3.4.0 with HSM 你好,@jbhaijy如何用 hsm 获取最新的 cst,无法找到最新的。 Re: CST3.4.0 with HSM 你好@jbhaijy、 您能否尝试对 openssl.cnf 文件进行以下更改? openssl_conf = openssl_def [openssl_def] engines = engine_section [engine_section] pkcs11 = pkcs11_section [pkcs11_section] engine_id = pkcs11 #Path to the Compiled OpenSSL PKCS11 from OpenSC - libp11 dynamic_path = /usr/lib/x86_64-linux-gnu/engines-1.1/libpkcs11.so MODULE_PATH = /home/jbhaijy/digicert/smtools-linux-x64/smpkcs11.so init = 0 如果问题得到解决,请告诉我。 致以最崇高的敬意, Hector。 Re: CST3.4.0 with HSM 你好@hector_delgado 我按照 AN12812 中提到的步骤进行了操作,但我们使用的不是软 HSM,而是第三方 HSM。 可能的原因是什么? 此致, jbhaijy Re: CST3.4.0 with HSM 你好@jbhaijy、 您是否遵循了我们的应用笔记使用带有硬件网络安全模块的代码签名工具 (https://www.nxp.com/webapp/Download?colCode=AN12812& location =null) 中的所有步骤? 尽管这是一份旧指南,但我相信它仍然应该适用于我们当前的CST版本。 如果有帮助,请告诉我。 致以最崇高的敬意, Hector。 Re: CST3.4.0 with HSM @hector_delgado 感谢您的答复。 我们希望为 i.MX6& i.MX8 提供 CST 签名解决方案。两者都是自定义板。我运行的是 Ubuntu-22.04 虚拟机。 Re: CST3.4.0 with HSM 你好@jbhaijy、 希望你一切都好! 您使用的是哪种 i.MX?是定制板还是我们的 EVK?另外,您在主机环境中使用的是哪个发行版和版本的 Linux? 致以最崇高的敬意, Hector。
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Originality Signature Verification NTAG 424 DNA How to verify the Originality Signature using a Dynamic link that has Encrypted PICC Data (UID, Counter) and CMAC?  Re: Originality Signature Verification NTAG 424 DNA Hi, I have posted in the forum and made a ticket for a similar issue but have not received an answer. Can you DM me please? Re: Originality Signature Verification NTAG 424 DNA Hi, In order to keep only one channel of communication, we will continue the communication in your internal ticket. Have a nice day! Regards, Eduardo. Re: Originality Signature Verification NTAG 424 DNA Hello, My request is not to verify it using the TagXplorer or RFIDDiscover. My query is how do we do this via program/script/code.  I don’t think the Reader is of an Essence here as I have successfully retrieved the UID, and Signature from the Tag. What I need is a program or script or guide on how to verify the Asymmetric Signature. Thanks Re: Originality Signature Verification NTAG 424 DNA Hi, By any chance, are you using any of our NFC Readers? The full version of RFIDDiscover software should include Signature Verification, and I will recommend you testing the Signature Verification by using our supported readers. Regards, Eduardo. Re: Originality Signature Verification NTAG 424 DNA Hello @EduardoZamora , Thanks for your reply.  I'm aware of the following Details. I'm trying to do the asymmetric originality signature validation. I have the UID and the Signature from the Tag which I get using the Read_Sig command. However when I use the Private key mentioned in the 8.2 of the AN12196, I'm getting signature fail.  I have also tried the Example given in the AN260412. Under the 2.2.1.3 C code example. I'm still getting the Tag Failed when I replace the Values of my Tag Signature. Please need help with this as it is crucial. Thanks  Re: Originality Signature Verification NTAG 424 DNA Hello @yosuf Hope you are doing well. Originality Signature Verification could be checked based on the secret originality keys (Symmetric check) or based on the NXP Originality Signature, computed over the UID (Asymmetric check). More information on this can be found in NTAG 424 Data Sheet, Section 10.10 Originality check commands; and NTAG 424 DNA and NTAG 424 DNA TagTamper features and hints, Section 8 Originality Signature Verification, together with an example. Regards, Eduardo.
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S32K14X_MCAL4_2_RTM_1_0_0 このバージョンのサンプルが他にもたくさんあるので、この autosar mcal コンポーネント「 S32K14X_MCAL4_2_RTM_1_0_0.exe 」が欲しいのですが、NXP の Web サイトで見つけることができません。どなたか教えていただけませんか? Re: S32K14X_MCAL4_2_RTM_1_0_0 こんにちは@wuki 、 前述したように、 NXP.comで「S32K1 MCAL」パッケージを検索できます。「ダウンロード」をクリックするとFlexeraポータルにリダイレクトされ、 S32K14X_MCAL4_2_RTM_1_0_0.exeをダウンロードできます。 Snag_12eaa4ac.png よろしくお願いします、 ジュリアン Re: S32K14X_MCAL4_2_RTM_1_0_0 この AUTOSAR mcal コンポーネント「 S32K14X_MCAL4_2_RTM_1_0_0.exe 」も欲しいのですが、手伝っていただけますか? Re: S32K14X_MCAL4_2_RTM_1_0_0 こんにちは@Li-1948さん、 NXP.com ページで S32K1 MCAL を検索すると見つかります。次のリンクからダウンロードできます: SW32K14-MCAL421-RTMC-1.0.0。 よろしくお願いします、 ジュリアン
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Problems Setting Prescaler for PWM capture We are using a PWM input to capture a external frequency of a tacho. With the standard settings everything works fine but when i apply a prescaler during initialization pwmConfig.prescale = kPWM_Prescale_Divide_64; or by setting it via void PWM_SetClockMode the values of CVAL2 and CVAL3 are always 0x00 and the counter is not counting My signal has a frequency of 200Hz  Re: Problems Setting Prescaler for PWM capture Hello, I've encountered the same issue, when configuring the any of the four PWM peripherals clock perscaler with values other than kPWM_Prescale_Divide_1 , the counter of the selected PWM peripheral doesn't work at all. I'm using the imxrt1062 processor and MCUXpresso IDE v11.9.1 I hope, you can support me as soon as possible. And, here is a snippet of my code where I configure and initialize the pwm peripherals. static void pwm_init(void) { pwm_config_t pwmConfig; pwm_input_capture_param_t captureConfig; pwm_fault_param_t faultConfig; /* Read the PWM default configuration */ PWM_GetDefaultConfig(&pwmConfig); pwmConfig.clockSource = kPWM_BusClock; pwmConfig.prescale = kPWM_Prescale_Divide_2; pwmConfig.pairOperation = kPWM_Independent; pwmConfig.initializationControl = kPWM_Initialize_LocalSync; pwmConfig.reloadLogic = kPWM_ReloadImmediate; pwmConfig.reloadSelect = kPWM_LocalReload; pwmConfig.reloadFrequency = kPWM_LoadEveryOportunity; pwmConfig.forceTrigger = kPWM_Force_LocalSync; pwmConfig.enableDebugMode = true; PWM_Init(PWM1_BASEADDR, kPWM_Module_3, &pwmConfig); PWM_Init(PWM2_BASEADDR, kPWM_Module_3, &pwmConfig); PWM_Init(PWM3_BASEADDR, kPWM_Module_1, &pwmConfig); PWM_Init(PWM4_BASEADDR, kPWM_Module_1, &pwmConfig); // fault configuration PWM_FaultDefaultConfig(&faultConfig); /* Sets up the PWM fault protection */ PWM_SetupFaults(PWM1_BASEADDR, kPWM_Fault_0, &faultConfig); PWM_SetupFaults(PWM1_BASEADDR, kPWM_Fault_1, &faultConfig); PWM_SetupFaults(PWM1_BASEADDR, kPWM_Fault_2, &faultConfig); PWM_SetupFaults(PWM1_BASEADDR, kPWM_Fault_3, &faultConfig); /* Set PWM fault disable mapping for submodule 0/1/2 */ PWM_SetupFaultDisableMap(PWM1_BASEADDR, kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR, kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR, kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM1_BASEADDR, kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); /* Sets up the PWM fault protection */ PWM_SetupFaults(PWM2_BASEADDR, kPWM_Fault_0, &faultConfig); PWM_SetupFaults(PWM2_BASEADDR, kPWM_Fault_1, &faultConfig); PWM_SetupFaults(PWM2_BASEADDR, kPWM_Fault_2, &faultConfig); PWM_SetupFaults(PWM2_BASEADDR, kPWM_Fault_3, &faultConfig); /* Set PWM fault disable mapping for submodule 0/1/2 */ PWM_SetupFaultDisableMap(PWM2_BASEADDR, kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR, kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR, kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM2_BASEADDR, kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); /* Sets up the PWM fault protection */ PWM_SetupFaults(PWM3_BASEADDR, kPWM_Fault_0, &faultConfig); PWM_SetupFaults(PWM3_BASEADDR, kPWM_Fault_1, &faultConfig); PWM_SetupFaults(PWM3_BASEADDR, kPWM_Fault_2, &faultConfig); PWM_SetupFaults(PWM3_BASEADDR, kPWM_Fault_3, &faultConfig); /* Set PWM fault disable mapping for submodule 0/1/2 */ PWM_SetupFaultDisableMap(PWM3_BASEADDR, kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR, kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR, kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM3_BASEADDR, kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); /* Sets up the PWM fault protection */ PWM_SetupFaults(PWM4_BASEADDR, kPWM_Fault_0, &faultConfig); PWM_SetupFaults(PWM4_BASEADDR, kPWM_Fault_1, &faultConfig); PWM_SetupFaults(PWM4_BASEADDR, kPWM_Fault_2, &faultConfig); PWM_SetupFaults(PWM4_BASEADDR, kPWM_Fault_3, &faultConfig); /* Set PWM fault disable mapping for submodule 0/1/2 */ PWM_SetupFaultDisableMap(PWM4_BASEADDR, kPWM_Module_0, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR, kPWM_Module_1, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR, kPWM_Module_2, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); PWM_SetupFaultDisableMap(PWM4_BASEADDR, kPWM_Module_3, kPWM_PwmA, kPWM_faultchannel_0, kPWM_FaultDisable_0 | kPWM_FaultDisable_1 | kPWM_FaultDisable_2 | kPWM_FaultDisable_3); /* Configure the capture input of the PWM for one shot polling */ captureConfig.captureInputSel = true; captureConfig.edge0 = kPWM_RiseAndFallEdge; captureConfig.edge1 = kPWM_Disable; captureConfig.enableOneShotCapture = false; captureConfig.edgeCompareValue = 1; PWM_SetupInputCapture(PWM1_BASEADDR, kPWM_Module_3, kPWM_PwmA, &captureConfig); PWM_SetupInputCapture(PWM2_BASEADDR, kPWM_Module_3, kPWM_PwmA, &captureConfig); PWM_SetupInputCapture(PWM3_BASEADDR, kPWM_Module_1, kPWM_PwmA, &captureConfig); PWM_SetupInputCapture(PWM4_BASEADDR, kPWM_Module_1, kPWM_PwmA, &captureConfig); PWM_SetPwmLdok(PWM1_BASEADDR, kPWM_Control_Module_3, true); PWM_SetPwmLdok(PWM2_BASEADDR, kPWM_Control_Module_3, true); PWM_SetPwmLdok(PWM3_BASEADDR, kPWM_Control_Module_1, true); PWM_SetPwmLdok(PWM4_BASEADDR, kPWM_Control_Module_1, true); PWM_StartTimer(PWM1_BASEADDR, kPWM_Control_Module_3); PWM_StartTimer(PWM2_BASEADDR, kPWM_Control_Module_3); PWM_StartTimer(PWM3_BASEADDR, kPWM_Control_Module_1); PWM_StartTimer(PWM4_BASEADDR, kPWM_Control_Module_1); }   Problems Setting the Prescaler for PWM capture Hi, I have the same problem as the owner, when I remove the crossover code or set it to 1 crossover frequency, the Counter works fine, but when I set it to 2 crossover frequency or higher the Counter stops, what is the reason for this? void Capture_config(void) { pwm_input_capture_param_t pwm_input_capture; gpio_pin_config_t PWM_pin_config; //初始化输入捕获管脚 IOMUXC_SetPinMux(PWM2_PWMA03_IOMUXC, 0U); //设置外部引脚的复用功能 IOMUXC_SetPinConfig(PWM2_PWMA03_IOMUXC, PWMC_INPUT_PAD_CONFIG_DATA); //设置引脚的 pad 属性 PWM_pin_config.direction = kGPIO_DigitalInput; PWM_pin_config.interruptMode = kGPIO_NoIntmode; GPIO_PinInit(PWM2_PWMA03_GPIO, PWM2_PWMA03_GPIO_PIN, &PWM_pin_config); //初始化输入捕获配置参数 pwm_input_capture.captureInputSel = false; pwm_input_capture.edge0 = kPWM_RisingEdge; //pwm_input_capture.edge1 = kPWM_FallingEdge; pwm_input_capture.enableOneShotCapture = false; //pwm_input_capture.edgeCompareValue = 10; //当captureInputSel为FALSE时,此处设值无意义 pwm_input_capture.fifoWatermark = 0; PWM_SetupInputCapture(PI_PWM_BASEADDR, kPWM_Module_3, kPWM_PwmA, &pwm_input_capture); //开启捕获中断 //set_IRQn_Priority(PWM2_3_IRQn,Group4_PreemptPriority_0, Group4_SubPriority_0);//设置中断优先级 //PWM_EnableInterrupts(PI_PWM_BASEADDR, kPWM_Module_3, kPWM_CaptureA0InterruptEnable| kPWM_CaptureA1InterruptEnable ); PWM_EnableInterrupts(PI_PWM_BASEADDR, kPWM_Module_3, kPWM_CaptureA0InterruptEnable ); EnableIRQ(PWM2_3_IRQn); } /** * @brief 初始化 PWM 配置参数 * @retval 无 */ void PWM_config(void) { pwm_config_t pwmConfig;//定义pwm 配置结构体 PWM_Deinit(PI_PWM_BASEADDR, kPWM_Module_3); /*设置AHB总线时钟和IP总线时钟*/ CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ /*设置pwm 错误输入为高电平,表示没有错误,只有当pwm 没有错误输入或者禁止错误检测才能正常输出pwm波*/ XBARA_Init(XBARA1); XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault0); XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault1); XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault2); XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault3); PWM_GetDefaultConfig(&pwmConfig); pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle; //新值在上一个pwm周期输出结束之后加载到缓冲寄存器中 pwmConfig.pairOperation = kPWM_Independent; // 工作在独立模式 pwmConfig.clockSource = kPWM_BusClock; pwmConfig.enableDebugMode = true; // 使能DebugMode pwmConfig.prescale = kPWM_Prescale_Divide_128; //1320000000/128/65535=16Hz=PWM最小频率 //初始化 PWM 并且判断初始化是否成功 if (PWM_Init(PI_PWM_BASEADDR, kPWM_Module_3, &pwmConfig) == kStatus_Fail) { PRINTF("PWM initialization failed\n"); } Capture_config(); PWM_SetPwmLdok(PI_PWM_BASEADDR,kPWM_Control_Module_3 , true); PWM_StartTimer(PI_PWM_BASEADDR, kPWM_Control_Module_3 ); } Re: Problems Setting Prescaler for PWM capture Hello @mexp2, First of all, we apologize for the delay to answer you. Just for double check, could you please tell us where are you placing the kPWM_Prescale_Divide_128? It might be good if you could write the pwmConfig.prescale=kPWM_Prescale_Divide_128; after pwmConfig.pairOperation=kPWM_Independent; and before PWM_Init(). Also, which clock source are you using? Finally, could you please try to use other values of the prescaler below 64? Best regards, Raul. Re: Problems Setting Prescaler for PWM capture We use the imxRT1062 with the SDK v 2.13.0 /* Read the PWM default configuration */ PWM_GetDefaultConfig(&pwmConfig); pwmConfig.reloadLogic = kPWM_ReloadImmediate; pwmConfig.pairOperation = kPWM_Independent; pwmConfig.enableDebugMode = true; /* Init the pwm */ if( PWM_Init(TACHOPUMP_PERIPHERAL, TACHOPUMP_CHANNEL, &pwmConfig) == kStatus_Fail) { PRINTF("Can't initialize PWM\n"); return; } /* Configure the capture input of the PWM for one shot polling */ pwm_input_capture_param_t captureConfig; captureConfig.captureInputSel = false; captureConfig.edge0 = kPWM_RisingEdge; captureConfig.edge1 = kPWM_RisingEdge; captureConfig.enableOneShotCapture = true; PWM_SetupInputCapture(TACHOPUMP_PERIPHERAL, TACHOPUMP_CHANNEL, TACHOPUMP_SIGNAL, &captureConfig); PWM_SetPwmLdok(TACHOPUMP_PERIPHERAL, timerBitmask, true); PWM_StartTimer(TACHOPUMP_PERIPHERAL, timerBitmask); with this code everything works as expected, but if i add a prescaler in the configuration pwmConfig.prescale = kPWM_Prescale_Divide_128; the counter is not counting anymore Re: Problems Setting Prescaler for PWM capture Hi @mexp2 , I hope you are doing well. Please specify which i.MX Processor is used to debug further. Thanks & Regards, Sanket Parekh
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S32K311_UDS_Bootloader 你好 我正试图在 S32K311 中实现 UDS 引导加载器,具体方法请参考下面链接中的 S32K344 示例。 统一引导加载器演示 - NXP 社区 一切正常,传输数据完成后,启动尝试在 gs_stbootInfo 结构中写入下载状态和 CRC。 但在访问这个变量地址时,我收到了 harfault 错误。我还在链接文件中创建了 exchange_info 块。 但我不确定内存是在哪里初始化的。 nirmal_masilamani_0-1753105829794.png Re: S32K311_UDS_Bootloader 你好@lukaszadrapa、 感谢您的支持。 根据您的建议进行修改后,它成功了 Re: S32K311_UDS_Bootloader 你好@nirmal_masilamani 请看一下这个主题,我想这就是原因所在: https://community.nxp.com/t5/S32K/S32K3-sharing-data-between-Bootloader-and-Application/m-p/1502773 此致, Lukas
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使用 LS1028A 板上的 CAAM 硬件对明文执行 AES-GCM 加密和解密 我正在为Layerscape板开发网络安全引擎(CAAM)驱动程序。我目前正在寻找以下操作的指导或源代码参考:   我想创建一个黑钥匙,并用它对明文进行 AES-GCM 加密/解密。 我已经能够使用 AES-CCM 成功生成黑密钥。但是,我需要使用AES-GCM算法加密和解密明文,而且我找不到任何示例代码或明确的步骤来版本所需的任务描述符。   虽然 Linux 内核源代码包含构建共享描述符的代码,但我需要为该操作创建一个非共享(简单)描述符。   此外,谁能解释一下如何正确使用黑钥匙来使用 AES-GCM 加密和解密数据?具体来说   - 如何在描述符中加载黑键和键修改器。 - CAAM 如何在内部使用此密钥进行 GCM 加密/解密。   任何参考链接或工作示例将不胜感激。 Re: Perform AES-GCM encryption and decryption of plaintext using the CAAM hardware on the LS1028A bo 谢谢,@Oswalag 我在 https://gitlab.navisincontrol.com/varigit/linux-imx/-/blob/lf-5.15.y_var01/drivers/crypto/caam/caamkeyblob.c 找到了 黑钥 的好参考资料,在 https://github.com/nxp-mcuxpresso/mcux-sdk/blob/main/drivers/caam/fsl_caam.c 找到了 AES-GCM 的好参考资料 Re: Perform AES-GCM encryption and decryption of plaintext using the CAAM hardware on the LS1028A bo 你好 你可以找到关于如何生成黑钥的参考资料。 GitHub-nxp-imx/keyctl_caam:Keyctl CAAM 网络安全 在 dpaa 高效密码学标准(SEC)驱动程序中,DPDK 默认支持 AES_GCM。在 DPAA_SEC_AEAD 案例中,你可以参考关于构建描述符的 DPDK 源代码。 DPDK/drivers/crypto/dpaa_sec/dpaa_sec.c 您还可以在LS1028ASECRM中找到更多信息。
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IMX8ULP:带 EPDC 显示屏的硬件加速功能 你好, 我正在使用连接到 IMX8ULP 的 EPDC 显示界面。EPDC 显示屏的驱动程序基于 FBDEV。由于 FBDEV 仅支持软件渲染,因此目前 CPU 负载超过 100% 。关于 EPDC 显示屏的支持,我有以下疑问: 1.EPDC 是否只支持 FBDEV?是否有任何驱动程序或修补程序可利用 DRM 对 EPDC 进行管理?与 DRM 一样,我们可以使用 GLES 进行硬件加速。 2. 3. 使用 FBDEV 为 EPDC 显示屏进行渲染时,有什么最佳方法可以避免 CPU 负载过高? Regards, Bhavin #IMX8ULP Re: IMX8ULP : Hardware acceleration with EPDC display 嗨,@Bhavin-Sharma、 能否请您联系当地的恩智浦 FAE,以便我们提供更多帮助? 谨致问候, Chong Re: IMX8ULP : Hardware acceleration with EPDC display 我参考了所附的链接,但没有找到任何与在 EPDC 显示屏上使用 DRM 有关的声明。 能否请您分享一下您所分享的 PDF 链接中证实支持它的确切章节或声明? 感谢你的支持 Re: IMX8ULP : Hardware acceleration with EPDC display 你好 是的,两者都支持,请查看 iMX linux 的版本说明 https://www.nxp.com/docs/en/release-note/RN00210.pdf 此致 Re: IMX8ULP : Hardware acceleration with EPDC display 我验证了我正在为我的电路板支持包设置克隆的源代码,它是恩智浦的官方GitHub仓库。此外,styhead 分支只支持 6.12.3 内核,而 6.12.20 内核由 walnascar 提供。 我尝试过这两个分支,但它们都不支持用于 EPDC 显示的 DRM。你能提供任何链接或资料来源来证明这一点吗? 此致, 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 你好 在恩智浦电路板支持包 6.12.20中,是的,它可以正常工作。 此致 Re: IMX8ULP : Hardware acceleration with EPDC display 你好,@Bio_TICFSL、 我切换到 yocto-styhead 分支,并检查了内核(6.12.3)源代码,发现它也只支持通过 FBDEV 显示 EPDC。 能否请您验证一次,并提供具有此支持的 yocto 分支的链接? 此致, 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 感谢@Chong 提供的补丁。 我这周休假,所以暂时无法测试。一旦完成,我一定会发布最新消息。 此致, 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 你好 恩智浦的 yocto 支持 EPDC 上的 DRM,但你使用的是社区电路板支持包,因为我们支持 6.12v 版本的 yocto Styhead 请更新你的 yocto。 此致 Re: IMX8ULP : Hardware acceleration with EPDC display Hi@Bhavin-Sharma, 附上的演示程序启用了 g2d,可以减少 CPU 负载。 您可以访问imx-LVGL-G2D-enablement 获取更多信息,但请注意此补丁仅适用于 LVGL 8.x 版本。 在 LVGL 9.3 中,G2D 默认已启用(在此查看)。它适用于 imx8ulp。 它需要一些将 EPD 面板移植到 FBdev 的知识。 我们还没有测试过复杂的动画(如渲染 3D 物体)。 如果您有需要,我们希望您能提供一个具体的测试,我们可以帮助您进行优化。 谨致问候, Chong Re: IMX8ULP : Hardware acceleration with EPDC display 我目前没有使用动画,只是尝试在显示屏上呈现多幅图像,放大或缩小。但是,如果能对动画进行测试,如在 glmark2-es2 实用程序中渲染 3D 物体,那将会很有帮助。 此致, 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 嗨,@Bhavin-Sharma、 对不起,我错过了信息。 我可以继续提供帮助。 我可以尝试提供一个基于 LVGL 并使用 G2D 加速的简单演示。 您的应用程序中使用了哪些变换(旋转/缩放/调整大小),或者是否有任何特殊的动画效果? 谨致问候, Chong Re: IMX8ULP : Hardware acceleration with EPDC display 您好, @Chong,我还在研究同样的问题,还没有找到解决方法。您能帮帮我吗? Re: IMX8ULP : Hardware acceleration with EPDC display 感谢您的及时回复,@Chong 在用户界面开发方面,我使用的是恩智浦本身支持的 GUI-guider 工具,LVGL 版本为 9.2。 目前,我无法共享任何代码,因为应用程序是专有的,而且简单的测试程序不会对 CPU 造成太大的负荷。 您能否提供一个使用 PXP 和 GPU 进行渲染并卸载 CPU 的应用程序示例? Regards、 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 嗨,@Bhavin-Sharma、 事实上,我们还没有发布过在 imx8ulp 上对 LVGL 进行 GPU/PXP 加速渲染的实例。不过,在 LVGL 程序中可以加速 2D GPU 和 PXP。我们可以通过修补来实现这一功能。您使用的是哪个版本的 LVGL?如果您能提供一个简单的测试程序,我们可以帮助您提高 imx8ulp 的性能。 谨致问候, Chong Re: IMX8ULP : Hardware acceleration with EPDC display 嗨,@Chong、 我使用的框架是 LVGL 来实现用户界面。到目前为止,我已经开发了 HDMI 显示器,以观察 FBDEV 的性能。我尚未迁移 EPDC 显示应用程序,可能需要几天时间。一旦我对显示屏进行了测试,我就会把它发布到这里。 我相信 LVGL 确实支持使用 PXP 进行渲染,但仅限于特定平台。这是真的吗? 此致, 巴文 Re: IMX8ULP : Hardware acceleration with EPDC display 嗨,@Bhavin-Sharma、 1.EPDC 是否只支持 FBDEV? 我们只提供基于 FBdev 的 EPDC 驱动程序。但也可以参考一些第三方 DRM 移植。保留 FBdev,因为它的 DRM EPD 性能更好。您只需将渲染的内存标记为 Framebuffer,然后提交上传即可。您的用户界面使用的是哪种显示框架(QT/LVGL/wayland)?您可以联系您的 FAE 获取更多支持。 2.有了 FBDEV,我还能以某种方式使用任何形式的硬件渲染吗? 您可以使用 GPU 和 PXP 来加速程序。只需将渲染内存指向帧缓冲器,然后提交 EPDC 更新即可。 3.使用 FBDEV 为 EPDC 显示屏进行渲染时,怎样才能避免 CPU 负载过高? imx8ulp 中有许多用于 EPD 渲染的硬件模块。您可以描述您实现的具体功能,或向我们提供测试程序,我们可以帮助您在 imx8ulp 中实现更好的性能。 谨致问候, Chong Re: IMX8ULP : Hardware acceleration with EPDC display 感谢您的回复,@Bio_TICFSL。 A1) 不,它支持 DRM,是的,它使用 GPU 加速。 我正在使用 YOCTO (Walnascar) 为 IMX8ULP 设置。它的内核是 6.12。我查看了一下,没有找到 EPDC 支持 DRM 的驱动程序。 其他内核版本是否支持?您能帮助我们了解为 EPDC 启用 DRM 支持的步骤吗? 致 Bhavin Re: IMX8ULP : Hardware acceleration with EPDC display 你好 A1) 不,它支持 DRM,是的,它使用 GPU 加速。 A2) 对不起,不是,应该是纯软件 A3) 只要禁用 GPU,所有渲染都将通过软件完成。 以下是 iMX8ULP 的 EPDC 连接方法: https://docs.nxp.com/bundle/MCIMX8ULP-EVK-UM/page/topics/electrophoretic_display_interface.html 此致
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[FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE I have a fatal error in STEP 4.1 Option #1: Get the App Software Pack with MCUXpresso IDE at https://github.com/nxp-appcodehub/ap-dvs-pvt-sensor/blob/mcux_release_github/dvs_pvt_sensor/app/evkmimxrt595/doc/evkmimxrt595_dvs_pvt_sensor_lab_guide.pdf This issue looks a similar issue that I reported at https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/can-t-download-mcu-examples-from-github/m-p/2138909#M34795 ==================STEP 4.1 Option command log====================== $west update === updating mcux-sdk (core): --- mcux-sdk: initializing Initialized empty Git repository in ~/nxp-githubs/appswpacks_dvs_pvt_sensor/core/.git/ --- mcux-sdk: fetching, need revision MCUX_2.11.0 remote: Enumerating objects: 80743, done. remote: Counting objects: 100% (7353/7353), done. remote: Compressing objects: 100% (917/917), done. error: RPC failed; curl 92 HTTP/2 stream 0 was not closed cleanly: CANCEL (err 😎 error: 6264 bytes of body are still expected fetch-pack: unexpected disconnect while reading sideband packet fatal: early EOF fatal: fetch-pack: invalid index-pack output FATAL ERROR: command exited with status 128: fetch -f --tags -- https://github.com/nxp-mcuxpresso/mcux-sdk MCUX_2.11.0 Re: [FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE Now it works after I reported it to our company IT. Thanks. Re: [FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE Hi @sukhwan , I just tried with the option 2, but looks like it works well as expected. Please kindly refer to the following for details. Kan_Li_0-1753683795617.png The command I tried on my side: Kan_Li_1-1753683829374.png Was there any network issue from your side? Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: [FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE Hi @sukhwan , May I have your MCUXpresso IDE version?  Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: [FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE ===========Step 4.2 Option 2 log================= Failed to execute command Cloning into '~/nxp/appswpacks-dvs-pvt-sensor/.west/manifest-tmp'... error: RPC failed; curl 56 GnuTLS recv error (-54): Error in the pull function. error: 3468 bytes of body are still expected fetch-pack: unexpected disconnect while reading sideband packet fatal: early EOF fatal: fetch-pack: invalid index-pack output FATAL ERROR: command exited with status 128: git clone --branch mcux_release_github https://github.com/NXPmicro/appswpacks-dvs-pvt-sensor ~/nxp/appswpacks-dvs-pvt-sensor/.west/manifest-tmp Re: [FATAL ERROR] Import the App Software Pack Into MCUXpresso IDE Step 4.2 Option 2 also has the same fatal error.
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MIFARE DESFire 附加访问权限 什么是 MIFARE DESFire 卡的附加访问权限及其编码方式?我现在才知道它们应该是 0xFFFF 的形式,但这意味着什么,它又赋予了我什么额外的权利? 入门指南
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